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參數(shù)資料
| 型號： | MX98728 |
| 英文描述： | GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| 中文描述： | GMAC的單芯片10/100快速以太網(wǎng)控制器的一般應(yīng)用程序 |
| 文件頁數(shù)： | 11/71頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MX98728 |
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11
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
GMAC Test Register A : TRA (Reg02h),R/W, default=00h
Bit
2.0
Symbol
TEST
Description
Test mode enable: Set to enable test modes defined by TMODE[2:0]. Default is reset
for the normal operation,
Test Mode Select bits[2:0]: Reserved for GMAC's internal tests, only meaningful when
the TEST bit is set, except when TMODE [2:0] = "110" which is also used as normal
mode with EEPROM interface disabled. When TMODE [2:0] = "110" & Test =0, then
MA19~MA16 are still SRAM address bit19~16, while Test = 1, MA19~MA16 are de-
fined as test pins reserved for debug purpose.
Receive Watchdog Release : When set, the receive watchdog is released 40 to 48 bit
times from the last carrier deassertion. When reset, the receive watchdog is released
16 to 24 bits times from the last carrier deassertion.
Receive Watchdog Disable : When set, the receive watchdog is disabled. When reset,
receive carriers longer than 2560 bytes are guaranteed to cause the watchdog time-
out. Packets shorted than 2048 bytes are guaranteed to pass.
Forced Collision : Set to force collision at every transmit packet. This bit works only
in the internal FIFO loopback mode, i.e. LB0=1, LB1=0, to test the excessive colli-
sion. Default is reset.
Start/Stop Back-off counter: When set, indicates the internal back-off counter stops
counting when any carrier is detected. The counter resumes when the carrier drops.
When reset, the internal back-off counter is not affected by the carrier activity. Default
is reset.
2.1-2.3
TMODE[2:0]
2.4
RWR
2.5
RWD
2.6
FC
2.7
SB
GMAC Test Register B : TRB (Reg03h),R/W, default=00h
Bit
3.0
Symbol
FKD*
Description
Flaky Oscillator Disable: When set, indicates that the internal flaky
oscillator is disabled. Pseudo random numbers are chosen instead of
fully random numbers, used for the internal diagnostic purpose. Set to
disable the normal clocking scheme in the timer's test. Reset to enable
the timer test. Default is reset.
Reserved for test
Reserved for test
Reserved for test
Normally used as BFS0 pin for test purpose, while in MII mode, it is
defined as MII management clock signal (MDC) to be used as a timing
reference of MDIO pin.
Normally used as BKCNTLB pin for test purpose, while in MII mode, it is
used to control the direction of MDIO pin. Set MDIOEN = 1 will make
MDIO pin as input pin, the value can be read from MDI bit.
Set MDIOEN = 0 will make MDIO pin as output pin, the value of MDO bit
is driven out to MDIO pin.
3.1
3.2
3.3
3.4
RDNCNTCB*
RDNCNTSB*
COLCNTCB*
BFS0*(MDC)
3.5
BKCNTLB*(MDIOEN)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MX98728AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
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| MX98741 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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