參數(shù)資料
型號: MX98728
英文描述: GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION
中文描述: GMAC的單芯片10/100快速以太網(wǎng)控制器的一般應用程序
文件頁數(shù): 10/71頁
文件大?。?/td> 389K
代理商: MX98728
10
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
Network Control Register B : NCRB (Reg1h),R/W, default=01h
Bit
1.0
Symbol
PR*
Description
Promiscuous mode: Set to receive any incoming valid frames received, regardless of
its destination address. Default is set.
CApture Effect Mode: Set to enable an enhanced pick-off algorithm to avoid the net-
work capture effect.
Pass Multicast: Set to accept all multicast packets (not including the broadcast ad-
dress). Default is reset which directs all multicast address to hash table for further
filtering .
Pass Bad Frame: Set to enable GMAC to accept Runt frames defined by register 50.2
( RUNTSIZE). Default is reset. When PB=1, runt frame is accepted reguardless of
Reg32.3 (ARXERRB).
Accept Broadcast: Default is reset which yields control of all the broadcast addresses
to the check logic defined by register 32h bit 7, register 38h and 39h. Set to accept all
broadcast packets without any further address filtering.
Reserved for test purpose. Default is 0.
RXINTC[1:0]* Receive Interrupt Counter : Receive interrupt RI or REI assertion depends on the num-
ber of packets received defined by these two bits or the RXINTT timer ( Reg.15/14h )
timeout, whichever comes first.
1.1
CA*
1.2
PM*
1.3
PB*
1.4
AB*
1.5
1.7-6
HBD*
Default is 00h after reset, meaning the normal receive interrupt operation which as-
serts RI or REI after a single packet is received and no RXINTT timer is used. Non-
zero value in these two bits will enable this special receive interrupt operation.
RXINTC1 RXINTC0
Interrupt received packet count
0
0
1 ( default )
0
1
2
1
0
4
1
1
8
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