參數(shù)資料
型號(hào)： MX98728
英文描述： GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION
中文描述： GMAC的單芯片10/100快速以太網(wǎng)控制器的一般應(yīng)用程序
文件頁(yè)數(shù)： 30/71頁(yè)
文件大?。?/td> 389K
代理商： MX98728
30
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
4.1 Packet Transmission
GMAC supports two ways to prepare packet(s) for trans-
mission. One way is the host can write a packet directly
into the TX FIFO through an IO port and send the packet
directly from the FIFO. This is called the direct FIFO
mode. The other way is to write packet(s) into the TX
buffer ring in the packet memory and activate the TX
local DMA to send out packet(s). Using the direct FIFO
mode can eliminate the TX local DMA completely, which
will leave the packet memory's total bandwidth to the
RX local DMA and the host. Therefore, receiving at the
full line speed is more achievable this way. The disad-
vantage is that only one packet is prepared and sent out
at a time. The next packet must wait until the current
packet is sent out and the FIFO is empty before it can
be moved into the TX FIFO. In another word, you can
not issue the multiple packet transmission with a single
command. But you still can prepare new packet(s) in
the TX buffer ring while a packet in the direct FIFO mode
is still active. Once the packet in the direct FIFO mode
is finished, you can active the TX DMA right away.
The TX local DMA mode is used between GMAC and
the packet memory during the transmission of the packet.
TRP ( Transmit Read Page pointer ) is used by the local
DMA to fetch the first page of the desired packet in the
packet memory. When GMAC receives a TX DMA send
command ( register 00h.ST1=0, ST0=1 ), data in the
packet memory will be moved into the GMAC's transmit
FIFO. GMAC will append preamble, sync and CRC fields
during the actual transmission. The advantage of this
mode is the multiple packets can be processed with a
single command. New packet(s) to the packet memory
can be prepared while the TX local DMA is active. There-
fore, potential higher throughout of the TX channel can
be achieved. The disadvantage is the packet memory
bandwidth is now shared by the host, the TX channel
and the RX channel. This means the bandwidth might
not be enough for all three to run at their full speeds
which may result in the TX FIFO underrun, or the RX
FIFO overrun and slow host accesses, especially in a
system where you only have an 8 bit packet memory.
It may be desirable to mix both the direct FIFO mode
and the TX local DMA mode so that the bandwidth of the
packet memory and the convenience of the concurrent
processing of multiple packets can be compromised to
achieve the best system performance. Cautions should
be taken when you use the mixed mode. Do not write
directly to the FIFO while the TX local DMA is active,
because such write will interfere with whichever packet
being transmitted in the FIFO. Do not activate the TX
local DMA while the direct FIFO send has not been fin-
ished for the current packet transmission. Register
00h.ST1 and ST0 bits are both command and status,
before the host issues any new packet send command
(the TX DMA poll or the TX FIFO send ). Always read
these two bits and make sure they are both 0, which
indicate a transmit channel IDLE ( the FIFO is also empty
). The rule of the mixed modes is always activating one
mode at a time. ST1 and ST0 must both be 0 before the
other mode is used.
Prior to the transmission in the direct FIFO mode
When ST1 and ST0 bits are both 0, the host can write a
packet no longer than 1518 bytes through an IO port
register located in 4Bh to 48h. It is called the
"WRTXFIFOD" port. GMAC will record the byte count.
Since the register WRTXFIFOD is a write only port, it
can not be read. Before the entire packet is completely
inside the FIFO, the host is allowed to do other opera-
tions except activating the TX local DMA. When TX byte
count is not multiple of host bus width, TXFIFOCNT and
TXFIFOCNTEN should be set. Issuing the TX DMA poll
command before current direct FIFO write operations or
the TX FIFO send completion will "corrupt" the current
packet inside the TX FIFO. When the entire packet is in
the FIFO, the host can issue ST1=1 and ST0=0 (the TX
FIFO send command ). When this packet is sent out
completely, the transmit status will be recorded in regis-
ter 04h and both ST1 and ST0 are cleared to 0 to indi-
cate the IDLE state.
Prior to the transmission in the TX local DMA
mode
The transmit descriptor located at the beginning of the
first page of the desired packet in the packet memory
must be properly set by the device driver prior to a trans-
mit command. By using TWP ( Transmit Write Page
Pointer ) and the TWD data port , the device driver can
fill up packet(s) in the transmit buffer ring. For the single
packet transmission, the Next Packet Page Pointer field
of the transmit descriptor should be equal to the TRP
page pointer which links to the current packet itself. If
multiple packets are to be transmitted, then the Next
Packet Page Pointer field of the transmit descriptor should
be set to the start page of the next packet. The Current
Packet Length field ( in bytes ) is set to indicate the size
of the current packet. Transmit Status bit 7 ( the OWN
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