參數(shù)資料
型號： MX98728
英文描述： GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION
中文描述： GMAC的單芯片10/100快速以太網(wǎng)控制器的一般應(yīng)用程序
文件頁數(shù)： 23/71頁
文件大?。?/td> 389K
代理商： MX98728
23
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
MISC Control Register : MISC1, Reg3Dh, R/W, default=3Ch
Bit
3D.0
3D.1
Symbol
BURSTDMA
DISLDMA*
Description
reserved for internal DMA burst control, default = 0 after reset.
Disable Local DMA arbitration : Default is 0 after reset, meaning local DMAs are
enabled in the SRAM bus arbitration. Set to disable the local DMA arbitration only
when the Reg02h.0 TEST bit is also set. It is used to force the overrun or the
underrun error for the test purpose.
10 Base-T Port Full Duplex capability bit in the linkcode word : Default is set to
enable advertising the 10 Base-T Full duplex capability. Reset to disable advertis-
ing this capability in the outgoing NWAY's linkcode word.
10 Base-T Port Half Duplex capability bit in the linkcode word : Default is set to
enable advertising the 10 Base-T Half duplex capability. Reset to disable advertis-
ing this capability in the outgoing NWAY's linkcode word.
100 Base-TX Full Duplex capability bit in the linkcode word : Default is set to enable
advertising the 100 Base-TX Full duplex capability. Reset to disable advertising
this capability in the outgoing NWAY's linkcode word.
100 Base-TX Half Duplex capability bit in the linkcode word ; Default is set to
enable advertising the 100 Base-TX Half duplex capability. Reset to disable adver-
tising this capability in the outgoing NWAY's linkcode word.
TX FIFO Reset control : Writing a 1 to this bit will clear the TX FIFO, reset all the
current TX FIFO's internal pointers and related byte counters and bring the TX DMA
back to the idle state. After reset this bit to 0, GMAC starts normal operation. If
current transmission takes too long due to collisions, the software can use this bit
to abort "current transmission" and bring GMAC's TX DMA back to idle state for a
fresh new transmission.
RX FIFO Reset control : Writing a 1 to this bit will clear the RX FIFO, reset all the
current RX FIFO's internal pointers and related byte counters and bring the RX
DMA back to the idle state. After reset this bit to 0, GMAC starts normal operation.
3D.2
TPF
3D.3
TPH
3D.4
TXF
3D.5
TXH
3D.6
TXFIFORST
3D.7
RXFIFORST
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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