參數(shù)資料
型號(hào)： MX98728
英文描述： GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION
中文描述： GMAC的單芯片10/100快速以太網(wǎng)控制器的一般應(yīng)用程序
文件頁(yè)數(shù)： 39/71頁(yè)
文件大小： 389K
代理商： MX98728
39
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
There are 4 bytes in a descriptor structure for both the transmit and the receive packets.The receive descriptor is
prepared by GMAC and is defined as follows :
bit 7
Next Packet Page Pointer ( bit 7-4 )
Packet Length ( bit 3-0 )
Packet Length ( bit 11-8 )
Receive Status ( bit 7-4 )
bit 0
Next Packet Page Pointer ( bit 3-0 )
Next Packet Page Pointer( bit 11-8 )
Packet Length ( bit 7-4 )
Receive Status ( bit 3-0 )
Receive status in the descriptor
Notes : This staus byte of last received packet is also copied to register 5 ( LRPS ).
bit #
0
1
2
Symbol
BF
CRC
FAE
Description
RX Packet Buffer Full Error : 1 indicates the RX packet buffer is full.
CRC error : caused by the corrupted data or dribble byte (s).
Frame Alignment Error : Dribble nibble (s). An FAE error might not cause a CRC error (e.g.
only a dribble nibble is detected by GMAC). An FAE error will not set the RERR bit.
FIFO Overrun
Receive Watchdog : Set to indicate the frame length exceeds 2048 bytes.
Multicast Frame address : Set to indicate the current frame has multicast address.
Runt Frame : Set to indicate a frame length less than 64 or 60 bytes as defined by
register 50.2 ( RUNTSIZE) , only meaningful when Reg00h.4 (PB bit) is set.
Receive Error : a logical OR of CRC, FO, BF, RW and RF bits.
3
4
5
6
FO
RW
MF
RF
7
RERR
Receive packet assembly format in the packet
memory
For the 16 bit SRAM interface :
D15
Descriptor Byte 1
Descriptor Byte 3
Destination Address Byte 1
Destination Address Byte 3
Destination Address Byte 5
Source Address Byte 1
Source Address Byte 3
Source Address Byte 5
Type/Length byte 1
Data byte 1
D8
D7
Descriptor Byte 0
Descriptor Byte 2
Destination Address Byte 0
Destination Address Byte 2
Destination Address Byte 4
Source Address Byte 0
Source Address Byte 2
Source Address Byte 4
Type/Length byte 0
Data byte 0
D0
For the 8 bit SRAM interface :
D7
Descriptor Byte 0
Descriptor Byte 1
Descriptor Byte 2
Descriptor Byte 3
Destination Address Byte 0
Destination Address Byte 1
Destination Address Byte 2
Destination Address Byte 3
Destination Address Byte 4
Destination Address Byte 5
Source Address Byte 0
Source Address Byte 1
Source Address Byte 2
Source Address Byte 3
Source Address Byte 4
Source Address Byte 5
Type/Length byte 0
Type/Length byte 1
Data byte 0
D0
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