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參數(shù)資料
| 型號： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 48/71頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MX98727 |
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48
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
6.0 Serial ROM ( EEPROM ) Interface
Serial ROM Connection
GMAC
EESC
EECK
EEDI
EEDO
Serial ROM
(Micro Wire)
SK
CS
DIN
DOUT
EEDO - Serial ROM (EEPROM) Data Out = Register
1Ch, bit 3
EEDI - Serial ROM (EEPROM) Data In = Register1Ch,
bit2
EECK - Serial ROM (EEPROM) Serial Clock = register
1Ch, bit 1
EECS - Serial ROM (EEPROM) Chip Select = register
1Ch, bit 0
EESEL - must be set to enable the EEPROM access
by register 1Ch, bit 4
Software Programming Interface
A read operation consists of three phases :
1. Command phase - 3 bits ( binary code of "110")
2. Address phase - 6 bits for 256- to 1K-bit ROMs ( C46/
C66 pin is high), 8 bits for 2K- to 4K-bit ROMs ( C46/
C66 is forced low )
3. Data phase - 16 bits for all type of EEPROMs.
These phases are generated through a sequence of writes
to 1Ch. In certain action, the driver must wait until the
minimum timing requirement for the serial ROM opera-
tion is met in order to advance to the next action.
The software sequence is available in the C source code
from MXIC.
A typical read cycle can look like this(EESEL bit is set
)
Write register 1Ch 10H ( >= 30ns )
Write register 1Ch 11H ( >= 50ns )
Write register 1Ch 13H ( >= 250ns )
Write register 1Ch 11H ( >= 100ns )
Write register 1Ch 15H ( >= 150ns )
Write register 1Ch 17H ( >= 250ns )
Write register 1Ch 15H ( >= 250ns )
Write register 1Ch 17H ( >= 250ns )
Write register 1Ch 15H ( >= 100 ns )
Write register 1Ch 13H ( >= 250 ns )
Write register 1Ch 11H ( >= 100ns )
Write register 1Ch 00H ( >= 150 ns )
Write register 1Ch 00H ( >= 250 ns )
Write register 1Ch 00H ( >= 100ns )
Write register 1Ch 03H ( >= 100ns )
Read register 1Ch.3 = DX ( >= 150ns )
Write register 1Ch 01H ( >= 250ns )
Write register 1Ch 00H ( >= 100ns )
END
A Write operation consist of three phases :
1. Command phase - 3 bits ( binary code of "110" )
2. Address phase - 6 bits for 256- to 1K-bit ROMs, 8 bits
for 2K- to 4K-bit ROMs.
3. Data phase - 16 bits.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MX98728 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98728AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| MX98728EC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98741 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| MX98742 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FEBC 100 Base Fast Ethernet Bridge Controller |
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