- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359265 > MX98727 SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER PDF資料下載
參數(shù)資料
| 型號(hào)： | MX98727 |
| 英文描述： | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| 中文描述： | 單芯片的PCI / CARDBUS快速以太網(wǎng)控制器 |
| 文件頁(yè)數(shù)： | 25/71頁(yè) |
| 文件大?。?/td> | 389K |
| 代理商： | MX98727 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)當(dāng)前第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)
25
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
Write TX FIFO Data Port Register : WRTXFIFOD[31:0] ( reg 4B-48h ), WO
Bit
48.7-0,
49.7-0
4A.7-0
4B.7-0
Symbol
WRTXFIFOD[31:0]
Description
Write TX FIFO Data Port : The 32 bit write only data port for the TX on-chip
FIFO in the direct FIFO mode. In the 32 bit mode, H16_32=0, the MSB byte
(byte 3) is Reg4Bh and the LSB byte (Byte 0) is Reg48h. In the 16 bit
mode, H16_32=1, Reg49h is the MSB byte (byte 1) and Reg48h is the LSB
byte (byte 0). An internal counter (TXFIFOBC) is used to keep track of the
total number of bytes written to the FIFO through this port before the host
issues reg00h.ST1=1, ST0=0 (the TX FIFO send command). Do not write
to this port when the TX local DMA is still active.
IO Read Data Port Register : IORD[31:0] ( reg 4C-4Fh ), RO
4C.7-0,
4D.7-0
4E.7-0
4F.7-0
IORD[31:0]
IO Read Data Port : The 32 bit read only data port that works with the
IORDP page pointer. In the 32 bit mode, H16_32=0, the MSB byte (byte 3)
is Reg4Fh and the LSB byte (byte 0) is Reg4Ch. In the 16 bit mode,
H16_32=1, Reg4Dh is the MSB byte (byte 1) and Reg4Ch is the LSB byte
(byte 0). An internal counter (IORDPBC) is used to keep track of the
current location within a particular page . For the system that does not
support the SRDY pin, the Register 3A.1 bit (STIORD/RRDYB ) can be
used to read this port in a hand shaking manner. To use register 3A.1 ,first
write 1 to register 3A.1. When the data is ready in this IORD port, register
3A.1 bit will be internally cleared to 0. So the host can read the register
3A.1 bit for 0 in order to know whether the data is ready or not. This IORD
can be used to fetch TX descriptors in a multiple packets send operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MX98742 | FEBC 100 Base Fast Ethernet Bridge Controller |
| MX98902A(PLCC) | LAN Node Controller |
| MX98902A(PQFP) | LAN Node Controller |
| MX98902A(SQFP) | LAN Node Controller |
| MX99011MC | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX98728 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98728AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| MX98728EC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| MX98741 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| MX98742 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FEBC 100 Base Fast Ethernet Bridge Controller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。