參數資料
型號： MX98727
英文描述： SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER
中文描述： 單芯片的PCI / CARDBUS快速以太網控制器
文件頁數： 29/71頁
文件大小： 389K
代理商： MX98727
29
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
4.0 Host Communication
GMAC and the device driver communicate through three
data structures :
* On chip registers described in Chapter 3.
* Descriptors and data buffers resides in the packet
memory.
* Direct data port with on the chip TX FIFO for the direct
packet transmission.
GMAC moves received data frames to the receive buffer
in the local packet memory and transmits data from the
transmit buffers in the local packet memory. All the page
pointers in the registers together with the descriptors
acts as pointers to these buffers in the packet memory.
Figure 4.0 depicts the general data structure of the packet
memory and page pointers.
There are two data buffers inside the packet memory,
i.e. the transmit buffer and the receive buffer. Packet
memory is partitioned into pages. Each page contains
exactly 256 bytes. A page pointer defined by registers
acts as the base address of the corresponding page.
By programming these page pointers, the size and the
area of the transmit buffer and the receive buffer can be
individually set to the desirable size and area.
The transmit and receive buffers must be contiguous
and separated by the BP ( Boundary Page pointer ) de-
fined in registers 0Ah and 0Bh. TLBP ( Transmit Low
Boundary Pointer ) defines the start page of the transmit
buffer. BP- 1 defines the end page of the transmit buffer.
If the current transmit process exceeds the end of the
BP- 1 page, it will be set to the start page pointed to by
TLBP, thus forms a "ring buffer" that logically links the
end page back to the start page of the transmit buffer.
The receive buffer has a similar structure as the trans-
mit buffer. The start page of the receive buffer is pointed
to by BP while the end page is pointed to by RHBP (
Receive High Boundary Page Pointer ). If the current
receive process exceeds the end of the end page pointed
to by RHBP, then it will be set to the start page pointed
to by BP, thus forms a "ring buffer" that logically links
the end page and the start page of the receive buffer.
A 1.6K bytes TX FIFO can also be used to send out a
packet directly from the FIFO. The register port
WRTXFIFOD ( 4Bh-48h ) can be used by the host to
write the packet data directly into the TX FIFO. After
moving one complete packet into the TX FIFO, the host
can issue a command (called the TX FIFO send com-
mand) to send out the packet stored in the TX FIFO.
This function can be used alternately with the other trans-
mission method that uses the TX buffer ring.
All incoming and outgoing packets are stored in these
buffers. A long packet may occupy multiple pages that
are contiguous. The descriptor is located at the begin-
ning of the first page of the packet. Normally there might
be some free space left in the last page of a multiple-
page packet which is called the fragment page. A new
packet must start from an empty page. The free space
inside those fragment pages can not be used.
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相關代理商/技術參數
參數描述
MX98728 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION
MX98728AEC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference
MX98728EC 制造商:MCNIX 制造商全稱:Macronix International 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION
MX98741 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
MX98742 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FEBC 100 Base Fast Ethernet Bridge Controller
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