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參數(shù)資料
| 型號： | MTC50150-TB-C2 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | ADSL GATEWAY PROCESSOR |
| 中文描述： | 寬帶網(wǎng)關(guān)處理器 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 151K |
| 代理商： | MTC50150-TB-C2 |
3/20
MTC50150
5
– ARM946ES RISC processor dedicated to network processing, API and DSL modem control
– Hardware ATM processor: SAR function with AAL5 processing
– Hardware packet processor: Ethernet MAC, learning and filter bridge
– One 10/100 Base-T Ethernet MACs with MII interface for external PHY or multi-port switch
– One 8 or 16-bit wide Flash port, ISA compatible for up to 16Mbyte addressable memory
– One 32-bit wide SDRAM interface with 32Mbyte addressable memory
– Interface to MTC20174 DynaMiTe ADSL analog front end (AFE) chip
– Multi-channel DMA engine integrated with peripherals
– Low power: 1.8V +/-10% core voltage, 3.3V +/- 10% I/O voltage
– 128 instructions (32 bits) of boot ROM
– GPIO with support LED
– Cc-based Multi ICE/compiler support with assembler and debugger
– Software chip and system simulators for software development and debug
– JTAG board-level test interface
– 140MHz system clock (processor cycle clock)
– Sleep mode with wake on LAN wake on WAN feature
– Programmable system frequency clock: 140, 105, 70, 35 and 129MHz (fall back mode).
HARDWARE FEATURES
6
The software is organized in 5 clusters:
SOFTWARE ARCHITECTURE
– User interface API
– System services
– Network services
– TCP/IP socket
– ATM encapsulation
A description of the cluster contents is given in the software features section.
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