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參數資料
| 型號： | MTC50150-TB-C2 |
| 廠商： | 意法半導體 |
| 英文描述： | ADSL GATEWAY PROCESSOR |
| 中文描述： | 寬帶網關處理器 |
| 文件頁數： | 15/20頁 |
| 文件大?。?/td> | 151K |
| 代理商： | MTC50150-TB-C2 |
15/20
MTC50150
GPIO2 /
PB0 /
FS IN #16
A13
B /
O /
I
PRB08DGZ
General Purpose Pin 2 /
Main Clock Control PB0 /
Full scan input chain 16 (A946ES)
GPIO1 /
SI_RCLK /
SER2nCTS /
TRACEPKT13 /
U_TXADDR4
F13
B /
I /
I /
O /
I
PRB08DGZ
General Purpose Pin 1 /
External UART Clock /
CleanDMEP Serial Interface 2 nCTS
/ ETM9 Trace packet 13 /
Utopia Transmit Address Bit 4
GPIO0 /
SER2nRTS /
TRACEPKT12 /
U_NOTTXREF
G16
B /
O /
O /
I
PRB08DGZ
General Purpose Pin 0 /
CleanDMEP Serial Interface 2 nRTS
/ ETM9 Trace packet 12 /
Utopia Transmit Reference Clock
SI Serial Interface (4)
SI_SIN /
SER1SI
C7
I
PDIDGZ
Serial Interface Serial Data Input /
CleanDMEP Serial Interface 1 – serial
input
SI_SOUT /
SER1SO
B8
O
PRT08DGZ
Serial Interface Serial Data Output /
CleanDMEP Serial Interface 1 – serial
output
SI_nRTS /
SER1nRTS
A8
O
PRT08DGZ
Serial Interface Not Ready To Send /
CleanDMEP Serial Interface 1 nRTS
SI_nCTS /
SER1nCTS
D7
I
PDIDGZ
Serial Interface Not Clear To Send /
CleanDMEP Serial Interface 1 nCTS
Miscellaneous Test Pins (2)
IDDQMode
C6
I
PDIDGZ
IDDQ mode activation
FSSHIFT
A6
ID
PDDWDGZ
Full Scan Shift Enable
Core Power Supply Pins (26) [1.8V]
VDD_CORE
F2,
K2,
R2,
P5,
N9,
R10,
R15,
L15,
E13,
B15,
D12,
B6,
B2
P
PVDD1DGZ
1.8V
Table 2. MTC50150 Pin list
(continued)
Name
Pin
B
Buffer Type
Description
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