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參數(shù)資料
| 型號： | MTC50150-TB-C2 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | ADSL GATEWAY PROCESSOR |
| 中文描述： | 寬帶網(wǎng)關(guān)處理器 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 151K |
| 代理商： | MTC50150-TB-C2 |
MTC50150
10/20
SD_DQM2
P7
O
PRT08DGZ
SDRAM Data Mask 2 (Byte Enable)
SD_DQM3
N7
O
PRT08DGZ
SDRAM Data Mask 3 (Byte Enable)
ARM/Miscellaneous Interface (4)
ARMDEBUG
B7
I
PDIDGZ
ARM Debug Test mode (multiplexes the
ARM TAP onto the JTAG pins)
Tied to ‘0’ in functional mode
FLASHBOOT /
PLL_CTR_RUN
A7
I
PDIDGZ
Boot from external Flash PROM rather
than from internal ROM
Starts/Stops the PLL test counter
Tied to ‘1’ in functional mode
BYPASSPLL /
FS IN #15
C5
I /
I
PDIDGZ
Bypass CPU clock generation PLL
Tied to ‘0’ in functional mode
Full scan input chain 15 (ARM946E)
UTOPIASEL
R13
ID
PDDWDGZ
Select external Utopia Interface of ADSL
core (Sachem_ip)
JTAG/Test Interface (5)
TCK
E3
IU
PDUWDGZ
Boundary ScanTest Clock
TDI
F3
IU
PDUWDGZ
Boundary Scan Test Data In
TDO
E1
OZ
PRT08DGZ
Boundary Scan Test Data Out
TMS
E4
IU
PDUWDGZ
Boundary Scan Test Mode Shift
NTRST
F4
ID
PDDWDGZ
Boundary Scan Reset
ISA-like Interface (42 )
ISA_nCS /
TRACEPORT9 /
U_NOTRXREF
H15
O
PRT08DGZ
ISA bus Chip Select / Address Enable /
ETM9 Trace port 9 /
Utopia Receive Reference Clock
ISA_nRD
B13
O
PRT08DGZ
ISA bus Read Strobe / Output Enable
ISA_nWR
C13
O
PRT08DGZ
ISA bus Write Strobe
ROM_nCS
A14
O
PRT08DGZ
Flash PROM Chip Select / Address
Enable
ROM_ADDR21 /
PLL_DIV_OUT/
TRACEPKT11 /
U_RXSOC
D14
O /
O /
O /
OZ
PRT08DGZ
Flash PROM Address Bit 21 /
Divided clock in PLL test mode /
ETM9 Trace packet 11 /
Utopia Receive Start Of Cell
ROM_ADDR20 /
PLL_NOM_OUT /
TRACEPKT10 /
U_RXCLAV
E15
O /
O /
O /
OZ
PRT08DGZ
Flash PROM Address Bit 20 /
PLL output clock in PLL test mode/
ETM9 Trace packet 10 /
Utopia Receive Cell Available
ROM_ADDR19 /
TRACEPKT9 /
U_TXCLAV
E16
O /
O /
OZ
PRT08DGZ
Flash PROM Address Bit 19 /
ETM9 Trace packet 9 /
Utopia Transmit Cell Available
Table 2. MTC50150 Pin list
(continued)
Name
Pin
B
Buffer Type
Description
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