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參數(shù)資料
| 型號(hào)： | MT9076 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | T1/E1/J1 3.3V Single Chip Transceiver(T1/E1/J1 3.3V 單片收發(fā)器) |
| 中文描述： | T1/E1/J1收發(fā)3.3V的單芯片收發(fā)器（T1/E1/J1收發(fā)3.3單片收發(fā)器） |
| 文件頁(yè)數(shù)： | 51/162頁(yè) |
| 文件大小： | 427K |
| 代理商： | MT9076 |
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Preliminary Information
MT9076
47
ram. The transmit AB/ ABCD signaling nibbles can be passed either via the micro-ports (for channels with bit 1
set high in the Per Time Slot Control Word - pages 7H and 8H) or through related channels of the CSTi serial
links, see “ST-BUS vs. DS1 to Channel Relationship(T1)” on page 25. The receive signaling bits are always
mapped to the equivalent ST-BUS channels on CSTo. Memory pages five and six contain the transmit AB or
ABCD nibbles and pages eight and nine the receive AB or ABCD nibbles for micro-port CAS access.
The serial control streams that contain the transmit / receive signaling information (CSTi and CSTo
respectively) are clocked at 2.048 Mhz. The number of signaling bits to be transmit / received = 24 (timeslots)
x 4 bits per timeslot (ABCD) = 24 nibbles. This leaves many unused nibble positions in the 2.048 Mhz CSTi /
CSTo bandwidth. These unused nibble locations are tristated. The usage of the bit stream is as follows: the
signaling bits are inserted / reported in the same CSTi / CSTo channels that correspond to the DS1 channels
used in DSTi / DSTo - see Table 6, “ST-BUS vs. DS1 to Channel Relationship(T1),” on page 25. The control bit
MSN (signaling Control Word, page 01H, address 14H) allows for the ABCD bit to use the most significant
nibble of CSTi / CSTo (MSN set high) or the least significant nibble (MSN set low). Unused nibbles and
timeslots are tristate. In order to facilitate multiplexing on the CSTo control stream, an additional control bit
CSToEn (signaling Control Word, page 01H, address 14H) will tristate the whole stream when set low. This
control bit is forced low with the reset pin. In the case of D4 trunks, only AB bits are reported. The control bits
SM1-0 allow the user to program the 2 unused bits reported on CSTo in the signaling nibble otherwise occupied
by CD signaling bits in ESF trunks.
A receive signaling bit debounce of 6 msec. can be selected (DBEn set high - signaling Control Word, page
01H, address 14H). It should be noted that there may be as much as 3 msec. added to this duration because
signaling equipment state changes are not synchronous with the D4 or ESF multiframe.
If multi - frame synchronization is lost (page 3H, address 10H, bit 6 MFSYNC = 1) all receive signaling bits are
frozen. They will become unfrozen when multi - frame synchronization is acquired (this is the same as terminal
frame synchronization for ESF links).
When the SIGI interrupt is unmasked, IRQ will become active when a signaling state change is detected in any
of the 24 receive channels. The SIGI interrupt mask is located on page 1, address 1EH, bit 0 (set high to
enable interrupt); and the SIGI interrupt vector is located on page 4, address 1EH.
11.2
Channel Signaling in E1 Mode
In E1 mode, when control bit TxCCS is set to one, the MT9076 is in Common Channel signaling (CCS) mode.
When TxCCS is low it is in Channel Associated signaling mode (CAS). The CAS mode ABCD signaling nibbles
can be passed either via the micro-ports (when RPSIG = 1) or through related channels of the CSTo and CSTi
serial links (when RPSIG = 0). Memory pages 09H and 0AH contain the receive ABCD nibbles and pages 05H
and 06H the transmit ABCD nibbles for micro-port CAS access.
In CAS operation, an ABCD signaling bit debounce of 14 msec. can be selected by writing a one to DBNCE
control bit. This is consistent with the signaling recognition time of ITU-T Q.422. It should be noted that there
may be as much as 2 msec. added to this duration because signaling equipment state changes are not
synchronous with the PCM 30 multiframe.
If multiframe synchronization is lost (page 03H, address 10H, when MFSYNC = 1) all receive CAS signaling
nibbles are frozen. Receive CAS nibbles will become unfrozen when multiframe synchronization is acquired.
When the CAS signaling interrupt is unmasked (page 01H, address 1EH, SIGI=0), pin IRQ (pin 12 in PLCC, 65
in LQFP) will become active when a signaling nibble state change is detected in any of the 30 receive
channels.
In CCS mode, the data transmit on channel 16 is either sourced from channel 16 data on DSTi or from the pin
CSTi. Data received from channel 16 is clocked out on CSTo (pin 5 in PLCC, pin 55 in LQFP). By dividing down
the extracted 2.048 MHz clock.
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PDF描述 |
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| MT9080B | SMX - Switch Matrix Module(用于消費(fèi)類轉(zhuǎn)換應(yīng)用的開(kāi)關(guān)矩陣模塊) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9076AB | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver |
| MT9076BB | 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays |
| MT9076BB1 | 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays |
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