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參數(shù)資料
| 型號： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁數(shù)： | 55/145頁 |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
17
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
PWR_ON#
O
Standby
PWR_ON# (Power On) is the output to the power supply that is used to con-
trol the main power sources to the system board. This pin is low during the
S0 and S1 ACPI power states and high during the S3, S4, and S5 ACPI power
states. PWR_ON# requires a weak external pull-up.
SB_POWER
OK
I
Standby
Power OK. When asserted, SB_POWEROK is an indication to the I/O Control-
ler that core power and PCLK have been stable for at least 1 ms.
SB_POWEROK can be driven asynchronously. When SB_POWEROK is
negated, the I/O Controller asserts P_RST#. P_RST# is de-asserted once
SB_POWEROK has been asserted for 1ms.
SUS_STAT#
O
Standby
Suspend Status. This signal is asserted by the I/O Controller to indicate that
the system will be entering a low power state soon. Devices with memory
that need to switch from normal refresh to suspend refresh mode can moni-
tor this. It can also be used by other peripherals as an indication that they
should isolate their outputs that may be going to powered-off planes.
SUS_STAT# is driven high in S0 and S1 states and low in S3, S4, and S5 states.
Power/System Management (continued)
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
Suspend Support Signals
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
CPUSTP#/
GPIO[21]
O
Standby
CPU Clock Stop. Output to the system clock generator to halt CPU clocks.
Optional GPIO.
DCSTP#/
GPIO[19]
O
Standby Optional GPIO.
PCISTP#/
GPIO[20]
O
Standby
PCI Clock Stop. Output to the system clock generator to halt PCI clocks.
Optional GPIO.
POS#
O
Standby
Powered on Suspend. POS is driven when the system is in a suspend state.
Driven low in S0 and S5 states. Driven high in S1, S3, and S4 states.
SOFF#
O
Standby
S4/S5 plane control. SOFF is driven low in S0, S1, and S3 states. SOFF is driven
high in S4 and S5 states
Reset and Clock Signals
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
CRESET#
O
VDD3.3
CPU Reset. Optional CPU reset for certain processors.
OSC_CLK
I
VDD3.3
Oscillator Clock. OSC_CLK is a 14.318 MHz clock for the internal timers and
ACPI timers. This clock is permitted to stop during S3 or lower power states.
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相關代理商/技術參數(shù) |
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|---|---|
| MT8LLN22NCNE-A | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET - Trays |
| MT8LLN22NCNE-A2 | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET AND MOTHERBOARD - Trays |
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