參數(shù)資料
型號： MT48H16M16LFFG
廠商： Micron Technology, Inc.
英文描述： MOBILE SDRAM
中文描述： 移動SDRAM
文件頁數(shù)： 15/58頁
文件大小： 1451K
代理商： MT48H16M16LFFG
15
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x16
MOBILE SDRAM
ADVANCE
13
RAS#
CAS#
ROW-
ADDRESS
MUX
CLK
CS#
WE#
CKE
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTER
8
C
D
A0-A12,
BA0, BA1
DQM0-
DQM3
13
ADDRESS
REGISTER
15
256
(x32)
8192
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 256 x 32)
BANK0
AROW-
LATCH
&
DECODER
8192
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ0-
DQ31
32
32
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
32
12
BANK1
BANK2
BANK3
13
8
2
4
4
2
REFRESH
COUNTER
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A0-A8: x16
A10
BA0,1
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
A9, A11: x16
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to the start address and
continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a READ command. In either case, a continu-
ous flow of data can be maintained. The first data ele-
ment from the new burst follows either the last ele-
ment of a completed burst or the last desired data ele-
ment of a longer burst that is being truncated. The new
READ command should be issued
x
cycles before the
clock edge at which the last desired data element is
valid, where
x
equals the CAS latency minus one.
READs
READ bursts are initiated with a READ command,
as shown in Figure 5.
The starting column and bank addresses are pro-
vided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric READ commands used in the following illustra-
tions, auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available fol-
lowing the CAS latency after the READ command. Each
subsequent data-out element will be valid by the next
positive clock edge. Figure 6 shows general timing for
each possible CAS latency setting.
Figure 5
READ Command
Figure 6
CAS Latency
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