參數(shù)資料
型號(hào)： MT48H16M16LFFG
廠商： Micron Technology, Inc.
英文描述： MOBILE SDRAM
中文描述： 移動(dòng)SDRAM
文件頁數(shù)： 1/58頁
文件大?。?/td> 1451K
代理商： MT48H16M16LFFG
1
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x16
MOBILE SDRAM
ADVANCE
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.
256Mb SDRAM PART NUMBERS
PART NUMBER
MT48V16M16LFFG
MT48H16M16LFFG
ARCHITECTURE
16 Meg x 16
16 Meg x 16
VDD
2.5V
1.8V
16 Meg x 16
4 Meg x 16 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
512 (A0–A8)
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
MOBILE SDRAM
PIN ASSIGNMENT (Top View)
54-Ball FBGA
FEATURES
Temperature Compensated Self Refresh (TCSR)
Fully synchronous; all signals registered on
positive edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
Self Refresh Mode
64ms, 8,192-cycle refresh
LVTTL-compatible inputs and outputs
Low voltage power supply
Deep Power Down
Partial Array Self Refresh power-saving mode
Industrial operating temperature (-40
o
C to +85
o
C)
OPTIONS
V
DD
/V
DD
Q
2.5V/1.8V
1.8V/1.8V
Configurations
16 Meg x 16 (4 Meg x 16 x 4 banks)
WRITE Recovery (
t
WR/
t
DPL)
t
WR = 2 CLK
Plastic Packages – OCPL
1
54-ball FBGA (8mm x 14mm)
Timing (Cycle Time)
8.0ns @ CL = 3 (125MHz)
10ns @ CL = 3 (100MHz)
MARKING
V
H
16M16
FG
1
-8
-10
NOTE
: 1. See page 58 for FBGA Device Marking Table.
KEY TIMING PARAMETERS
SPEED
GRADE
-8
-10
-8
-10
-8
-10
CLOCK
FREQUENCY
125 MHz
100 MHz
100 MHz
83 MHz
50 MHz
40 MHz
ACCESS TIME
CL=1* CL=2*
–
–
–
–
19ns
22ns
SETUP HOLD
TIME
2.5ns
2.5ns
2.5ns
2.5ns
2.5ns
2.5ns
CL=3*
7ns
7ns
–
–
–
–
TIME
1.0ns
1.0ns
1.0ns
1.0ns
1.0ns
1.0ns
–
–
8ns
8ns
–
–
*CL = CAS (READ) latency
MT48V16M16LFFG, MT48H16M16LFFG–
4 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
www.micron.com/dramds
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