參數(shù)資料
型號(hào): MSC8256TVT1000B
廠商: Freescale Semiconductor
文件頁數(shù): 54/70頁
文件大?。?/td> 0K
描述: IC DSP 6 CORE 1GHZ 783FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: StarCore
類型: SC3850 內(nèi)核
接口: 以太網(wǎng),I²C,PCI,RGMII,串行 RapidIO,SGMII,SPI,UART/USART
時(shí)鐘速率: 1.0GHz
非易失內(nèi)存: ROM(96 kB)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 2.50V
電壓 - 核心: 1.00V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Hardware Design Considerations
Freescale Semiconductor
58
2.
After the above rails rise to 90% of their nominal voltage, the following I/O power rails may rise in any sequence (see
Figure 34): QVDD, NVDD, GVDD1, and GVDD2.
Notes: 1.
If the M3 memory is not used, M3VDD can be tied to GND.
2.
If the HSSI port1 is not used, SXCVDD1and SXPVDD1 must be connected to the designated power supplies.
3.
If the HSSI port2 is not used, SXCVDD2 and SXPVDD2 must be connected to the designated power supplies.
4.
If the DDR port 1 interface is not used, it is recommended that GVDD1 be left unconnected.
5.
If the DDR port 2 interface is not used, it is recommended that GVDD2 be left unconnected.
3.1.4
Reset Guidelines
When a debugger is not used, implement the connection scheme shown in Figure 35.
When a debugger is used, implement the connection scheme shown in Figure 36.
Figure 34. Supply Ramp-Up Sequence
Figure 35. Reset Connection in Functional Application
Figure 36. Reset Connection in Debugger Application
VDD, MVDD, M3VDD
90%
NVDD, QVDD, GVDD1, GVDD2
On-board PORESET source
TRST
PORESET
MSC815x
(example: voltage monitor)
10
ΚΩ
On-board PORESET source
TRST
PORESET
MSC815x
(example: voltage monitor)
On-board TRST source
(example: OnCE)
VDDIO
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