參數(shù)資料
型號： MSC8256TVT1000B
廠商： Freescale Semiconductor
文件頁數(shù)： 21/70頁
文件大?。?/td> 0K
描述： IC DSP 6 CORE 1GHZ 783FCPBGA
標準包裝： 1
系列： StarCore
類型： SC3850 內(nèi)核
接口： 以太網(wǎng)，I²C，PCI，RGMII，串行 RapidIO，SGMII，SPI，UART/USART
時鐘速率： 1.0GHz
非易失內(nèi)存： ROM（96 kB）
芯片上RAM： 576kB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.00V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
28
2.5.1.3
DDR2/DDR3 SDRAM Capacitance
Table 8 provides the DDR controller interface capacitance for DDR2 and DDR3 memory.
Note:
At recommended operating conditions (see Table 3) with VDDDDR = 1.8 V for DDR2 memory or VDDDDR =1.5 V for
DDR3 memory.
2.5.1.4
DDR Reference Current Draw
Table 9 lists the current draw characteristics for MVREF.
Note:
Values when used at recommended operating conditions (see Table 3).
2.5.2
High-Speed Serial Interface (HSSI) DC Electrical Characteristics
The MSC8256 features an HSSI that includes two 4-channel SerDes ports used for high-speed serial interface applications (PCI
Express, Serial RapidIO interfaces, and SGMII). This section and its subsections describe the common portion of the SerDes
DC, including the DC requirements for the SerDes reference clocks and the SerDes data lane transmitter (Tx) and receiver (Rx)
reference circuits. The data lane circuit specifications are specific for each supported interface, and they have individual
subsections by protocol. The selection of individual data channel functionality is done via the Reset Configuration Word High
Register (RCWHR) SerDes Protocol selection fields (S1P and S2P). Specific AC electrical characteristics are defined in
2.5.2.1
Signal Term Definitions
The SerDes interface uses differential signalling to transfer data across the serial link. This section defines terms used in the
description and specification of differential signals. Figure 4 shows how the signals are defined. For illustration purposes only,
one SerDes lane is used in the description. Figure 4 shows the waveform for either a transmitter output (SR[1–2]_TX and
Table 8. DDR2/DDR3 SDRAM Capacitance
Parameter
Symbol
Min
Max
Unit
I/O capacitance: DQ, DQS, DQS
CIO
68
pF
Delta I/O capacitance: DQ, DQS, DQS
CDIO
—0.5
pF
Note:
Guaranteed by FAB process and micro-construction.
Table 9. Current Draw Characteristics for MVREF
Parameter / Condition
Symbol
Min
Max
Unit
Current draw for MVREFn
DDR2 SDRAM
DDR3 SDRAM
IMVREFn
—
300
250
μA
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