參數(shù)資料
型號: MSC8256TVT1000B
廠商: Freescale Semiconductor
文件頁數(shù): 49/70頁
文件大小: 0K
描述: IC DSP 6 CORE 1GHZ 783FCPBGA
標準包裝: 1
系列: StarCore
類型: SC3850 內(nèi)核
接口: 以太網(wǎng),I²C,PCI,RGMII,串行 RapidIO,SGMII,SPI,UART/USART
時鐘速率: 1.0GHz
非易失內(nèi)存: ROM(96 kB)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 2.50V
電壓 - 核心: 1.00V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
Electrical Characteristics
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
53
Figure 26 provides the AC test load for the SPI.
Figure 26. SPI AC Test Load
Figure 27 and Figure 28 represent the AC timings from Table 36. Note that although the specifications generally reference the
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 27 shows the SPI timings in slave mode (external clock).
Figure 27. SPI AC Timing in Slave Mode (External Clock)
Figure 28 shows the SPI timings in master mode (internal clock).
Figure 28. SPI AC Timing in Master Mode (Internal Clock)
2.6.7
Asynchronous Signal Timing
Table 35 lists the asynchronous signal timing specifications.
Table 37. Signal Timing
Characteristics
Symbol
Type
Min
Input
tIN
Asynchronous
One CLKIN cycle
Output
tOUT
Asynchronous
Application dependent
Note:
Input value relevant for EE0, IRQ[15–0], and NMI only.
Output
Z0 = 50 Ω
VDDIO/2
RL = 50 Ω
SPICLK (input)
tNEIXKH
tNEKHOV
Input Signals:
SPIMOSI
(See note)
Output Signals:
SPIMISO
(See note)
tNEIVKH
tNEKHOX
Note: measured with SPMODE[CI] = 0, SPMODE[CP] = 0
SPICLK (output)
tNIIXKH
tNIKHOV
Input Signals:
SPIMISO
(See note)
Output Signals:
SPIMOSI
(See note)
tNIIVKH
tNIKHOX
Note: measured with SPMODE[CI] = 0, SPMODE[CP] = 0
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