參數(shù)資料
型號(hào)： MSC8256TVT1000B
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 52/70頁(yè)
文件大小： 0K
描述： IC DSP 6 CORE 1GHZ 783FCPBGA
標(biāo)準(zhǔn)包裝： 1
系列： StarCore
類(lèi)型： SC3850 內(nèi)核
接口： 以太網(wǎng)，I²C，PCI，RGMII，串行 RapidIO，SGMII，SPI，UART/USART
時(shí)鐘速率： 1.0GHz
非易失內(nèi)存： ROM（96 kB）
芯片上RAM： 576kB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.00V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤(pán)
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Hardware Design Considerations
Freescale Semiconductor
56
3
Hardware Design Considerations
The following sections discuss areas to consider when the MSC8256 device is designed into a system.
3.1
Power Supply Ramp-Up Sequence
The following subsections describe the required device initialization sequence.
3.1.1
Clock, Reset, and Supply Coordination
Starting the device requires coordination between several inputs including: clock, reset, and power supplies. Follow this
guidelines when starting up an MSC8256 device:
PORESET and TRST must be asserted externally for the duration of the supply ramp-up, using the VDDIO supply.
TRST deassertion does not have to be synchronized with PORESET deassertion. However, TRST must be deasserted
before normal operation begins to ensure correct functionality of the device.
CLKIN should toggle at least 32 cycles before PORESET deassertion to guarantee correct device operation. The 32
cycles should only be counted from the time after VDDIO reaches its nominal value (see timing 1 in Figure 33).
CLKIN should either be stable low during ramp-up of VDDIO supply (and start its swings after ramp-up) or should
swing within VDDIO range during VDDIO ramp-up, so its amplitude grows as VDDIO grows during ramp-up.
Figure 33 shows a sequence in which VDDIO ramps-up after VDD and CLKIN begins to toggle with the raise of VDDIO supply.
Note:
For details on power-on reset flow and duration, see the Reset chapter in the MSC8256 Reference Manual.
Figure 33. Supply Ramp-Up Sequence with VDD Ramping Before VDDIO and CLKIN Starting With VDDIO
Vo
lt
a
g
e
Time
VDDIO Nominal
PORESET/TRST asserted
VDD Nominal
CLKIN starts toggling
VDD applied
PORESET deasserted
1
VDDIO applied
VDDIO = Nominal
VDD = Nominal
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