參數(shù)資料
型號(hào): MSC8256TVT1000B
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 40/70頁(yè)
文件大?。?/td> 0K
描述: IC DSP 6 CORE 1GHZ 783FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: StarCore
類型: SC3850 內(nèi)核
接口: 以太網(wǎng),I²C,PCI,RGMII,串行 RapidIO,SGMII,SPI,UART/USART
時(shí)鐘速率: 1.0GHz
非易失內(nèi)存: ROM(96 kB)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 2.50V
電壓 - 核心: 1.00V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
Electrical Characteristics
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
45
2.6.2.3
Serial RapidIO AC Timing Specifications
Note:
Specifications are valid at the recommended operating conditions listed in Table 3.
Table 27 defines the transmitter AC specifications for the Serial RapidIO interface. The AC timing specifications do not include
REF_CLK jitter.
Table 28 defines the Receiver AC specifications for the Serial RapidIO interface. The AC timing specifications do not include
REF_CLK jitter.
Table 27. Serial RapidIO Transmitter AC Timing Specifications
Characteristic
Symbol
Min
Typical
Max
Unit
Deterministic Jitter
JD
0.17
UI p-p
Total Jitter
JT
0.35
UI p-p
Unit Interval: 1.25 GBaud
UI
800 – 100ppm
800
800 + 100ppm
ps
Unit Interval: 2.5 GBaud
UI
400 – 100ppm
400
400 + 100ppm
ps
Unit Interval: 3.125 GBaud
UI
320 – 100ppm
320
320 + 100ppm
ps
Table 28. Serial RapidIO Receiver AC Timing Specifications
Characteristic
Symbol
Min
Typical
Max
Unit
Notes
Deterministic Jitter Tolerance
JD
0.37
UI p-p
1
Combined Deterministic and Random Jitter
Tolerance
JDR
0.55
UI p-p
1
Total Jitter Tolerance
JT
0.65
UI p-p
1, 2
Bit Error Rate
BER
10–12
——
Unit Interval: 1.25 GBaud
UI
800 – 100ppm
800
800 + 100ppm
ps
Unit Interval: 2.5 GBaud
UI
400 – 100ppm
400
400 + 100ppm
ps
Unit Interval: 3.125 GBaud
UI
320 – 100ppm
320
320 + 100ppm
ps
Notes:
1.
Measured at receiver.
2.
Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 18. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.
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