參數(shù)資料
型號: MSC8144E
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 150 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 55/80頁
文件大?。?/td> 2284K
代理商: MSC8144E
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
59
Figure 32 shows the RGMII AC timing and multiplexing diagrams.
GTX_CLK125 reference clock duty cycle
tG125H/tG125
47
53
%
Notes:
1.
At recommended operating conditions with LVDD of 2.5 V +/- 5%.
2.
This implies that PC board design will require clocks to be routed with no additional trace delay
3.
For 10 and 100 Mbps, tRGT scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.
4.
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned
between.
5.
Duty cycle reference is LVdd/2.
6.
This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7.
GCR4 should be programmed as 0x00048120.
Figure 32. RGMII AC Timing and Multiplexing s
Table 51. RGMII with No On-Board Delay AC Timing Specifications (continued)
Parameter/Condition
Symbol
Min
Typ
Max
Unit
GTX_CLK
tRGT
tRGTH
tSKEWT
TX_CTL
TXD[8:5]
TXD[7:4]
TXD[9]
TXERR
TXD[4]
TXEN
TXD[3:0]
(At Transmitter)
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CLK
(At PHY)
RX_CTL
RXD[8:5]
RXD[7:4]
RXD[9]
RXERR
RXD[4]
RXDV
RXD[3:0]
RXD[8:5][3:0]
RXD[7:4][3:0]
RX_CLK
(At PHY)
tSKEWR
tSKEWT
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