參數(shù)資料
型號: MSC8144E
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 150 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 52/80頁
文件大?。?/td> 2284K
代理商: MSC8144E
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
56
Figure 27 provides the AC test load.
Figure 28 shows the MII receive AC timing diagram.
2.7.10.4
RMII Transmit and Receive AC Timing Specifications
Table 48 provides the RMII transmit and receive AC timing specifications.
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
2—
ns
RX_CLK clock rise
tMRXR
1.0
4.0
ns
RX_CLK clock fall time
tMRXF
1.0
4.0
ns
Notes:
1.
Typical RX_CLK period (tMRX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.
2.
Program GCR4 as 0x00030CC3.
Figure 27. AC Test Load
Figure 28. MII Receive AC Timing
Table 48. RMII Transmit and Receive AC Timing Specifications
Parameter/Condition
Symbol 1
Min
Max
Unit
REF_CLK duty cycle
tRMXH/tRMX
35
65
%
REF_CLK to RMII data TXD[1–0], TX_EN delay
tRMTKHDX
210
ns
RXD[1–0], CRS_DV, RX_ER setup time to REF_CLK
tRMRDVKH
4.0
ns
RXD[1–0], CRS_DV, RX_ER hold time to REF_CLK
tRMRDXKH
2.0
ns
REF_CLK data clock rise
tRMXR
1.0
4.0
ns
REF_CLK data clock fall
tRMXF
1.0
4.0
ns
Typical REF_CLK clock period (tRMX) is 20 ns
Notes:
1.
Typical REF_CLK clock period (tRMX) is 20 ns
2.
Program GCR4 as 0x00001405
Table 47. MII Receive AC Timing Specifications (continued)
Parameter/Condition
Symbol 1
Min
Max
Unit
Output
Z0 = 50 Ω
VDD/2
RL = 50 Ω
RX_CLK
RXD[3:0]
tMRDXKH
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
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