參數(shù)資料
型號(hào): MSC8144E
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: 0-BIT, 150 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁(yè)數(shù): 30/80頁(yè)
文件大?。?/td> 2284K
代理商: MSC8144E
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0
Electrical Characteristics
Freescale Semiconductor
36
2.7.2
Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 20 shows the maximum frequency values for
internal (Core, Reference, Bus and DSI) and external (CLKIN, PCI_CLK_IN and CLKOUT. The user must ensure that
maximum frequency values are not exceeded.
2.7.3
Reset Timing
The MSC8144E has several inputs to the reset logic:
Power-on reset (PORESET)
External hard reset (HRESET)
External soft reset (SRESET)
Software watchdog reset
JTAG reset
RapidIO reset
Software hard reset
Software soft reset
All MSC8144E reset sources are fed into the reset controller, which takes different actions depending on the source of the reset.
The reset status register indicates the most recent sources to cause a reset. Table 22 describes the reset sources.
Figure 7. Start-Up Sequence with VDD Raised Before VDDIO with CLKIN Started with VDDIO
Table 20. Clock Frequencies
Characteristic
Symbol
MIN
Max
Unit
CLKIN frequency
FCLKIN
25
150
MHz
PCI_CLK_IN frequency
FPCI_CLK_IN
25
150
MHz
CLKIN duty cycle
DCLKIN
40
60
%
PCI_CLK_IN duty cycle
DPCI_CLK_IN
40
60
%
Table 21. Clock Parameters
Characteristic
Min
Max
Unit
CLKIN slew rate
1—
V/ns
PCI_CLK_IN slew rate
1
V/ns
Vo
lt
a
g
e
Time
3.3 V
VDDIO Nominal
PORESET/TRST asserted
VDD Nominal
CLKIN starts toggling
VDD applied
PORESET
1
VDDIO applied
1.0 V
VDDIO = Nominal
VDD = Nominal
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