參數(shù)資料
型號(hào)： MSC8144E
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 150 MHz, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁(yè)數(shù)： 25/80頁(yè)
文件大?。?/td> 2284K
代理商： MSC8144E
Electrical Characteristics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
31
2.6.2
Serial RapidIO DC Electrical Characteristics
DC receiver logic levels are not defined since the receiver is AC-coupled.
2.6.2.1
DC Requirements for SerDes Reference Clocks
The SerDes reference clocks SRIO_REF_CLK and SRIO_REF_CLK are AC-coupled differential inputs. Each differential
clock input has an internal 50
Ω termination to GND
SXC. The reference clock must be able to drive this termination. The
recommended minimum operating voltage is –0.4 V; the recommended maximum operating voltage is 1.32 V; and the
maximum absolute voltage is 1.72 V.
The maximum average current allowed in each input is 8 mA. This current limitation sets the maximum common mode input
voltage to be less than 0.4 V (0.4 V/50
Ω = 8 mA) while the minimum common mode input level is GND
SXC. For example, a
clock with a 50/50 duty cycle can be driven by a current source output that ranges from 0 mA to 16 mA (0–0.8 V). The input is
AC-coupled internally, so, therefore, the exact common mode input voltage is not critical.
Note:
This internal AC-couple network does not function correctly with reference clock frequencies below 90 MHz.
If the device driving the SRIO_REF_CLK inputs cannot drive 50
Ω to GND
SXC, or if it exceeds the maximum input current
limitations, then it must use external AC-coupling. The minimum differential peak-to-peak amplitude of the input clock is 0.4 V
(0.2 V peak-to-peak per phase). The maximum differential peak-to-peak amplitude of the input clock is 1.6 V peak-to-peak (see
Figure 5. The termination to GNDSXC allows compatibility with HCSL type reference clocks specified for PCI-Express
applications. Many other low voltage differential type outputs can be used but will probably need to be AC-coupled due to the
limited common mode input range. LVPECL outputs can produce too large an amplitude and may need to be source terminated
with a divider network to reduce the amplitude. The amplitude of the clock must be at least a 400 mV differential peak-peak for
single-ended clock. If driven differentially, each signal wire needs to drive 100 mV around common mode voltage. The
differential reference clock (SRIO_REF_CLK/ SRIO_REF_CLK) input is HCSL-compatible DC coupled or LVDS-compatible
with AC-coupling.
Figure 5. SerDes Reference Clocks Input Stage
2.6.2.2
Spread Spectrum Clock
SRIO_REF_CLK/ SRIO_REF_CLK is designed to work with a spread spectrum clock (0 to 0.5% spreading at 3033 kHz rate
is allowed), assuming both ends have same reference clock. For better results use a source without significant unintended
modulation.
SRIO_REF_CLK
50
Ω
50
Ω
GNDSXC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSC8144EC 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core Digital Signal Processor
MSC8144ESVT1000B 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA BOX - Trays 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144ESVT800A 制造商:Freescale Semiconductor 功能描述:DSP 32BIT 800MHZ 800MIPS 783FCBGA - Trays
MSC8144ESVT800B 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 800MHZ 800MIPS 783-PIN FCBGA EACH - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144ETVT1000A 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA - Bulk
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