參數(shù)資料
型號: MSC8144E
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 150 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 37/80頁
文件大?。?/td> 2284K
代理商: MSC8144E
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0
Electrical Characteristics
Freescale Semiconductor
42
Figure 11 provides the AC test load for the DDR bus.
2.7.5
Serial RapidIO Timing and SGMII Timing
2.7.5.1
AC Requirements for SRIO_REF_CLK and SRIO_REF_CLK
Table 29 lists AC requirements.
Figure 11. DDR AC Test Load
Table 29. SDn_REF_CLK and SDn_REF_CLK AC Requirements
Parameter Description
Symbol
Min
Typical
Max
Units
Comments
REFCLK cycle time
tREF
10 (8, 6.4)
ns
8 ns applies only to serial RapidIO system
with 125-MHz reference clock. 6.4 ns
applies only to serial RapidIO systems with
a 156.25 MHz reference clock.
Note:
SGMII uses the 8 ns (125 MHz)
value only.
REFCLK cycle-to-cycle
jitter
tREFCJ
80
ps
Difference in the period of any two
adjacent REFCLK cycles
Phase jitter
tREFPJ
–40
40
ps
Deviation in edge location with respect to
mean edge location
Output
Z0 = 50 Ω
RL = 50 Ω
VDD/2
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