參數(shù)資料
型號(hào)： MSC8144E
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 150 MHz, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁(yè)數(shù)： 42/80頁(yè)
文件大?。?/td> 2284K
代理商： MSC8144E
Electrical Characteristics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
47
Total Jitter Tolerance
JT
0.65
UIPP
Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 14. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew
SMI
24
ns
Skew at the receiver input between lanes of a
multilane link
Bit Error Rate
BER
10–12
Unit Interval
UI
800
ps
±100 ppm
Table 38. Receiver AC Timing Specifications—2.5 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential Input Voltage
VIN
200
1600
mVPP
Measured at receiver
Deterministic Jitter Tolerance
JD
0.37
UIPP
Measured at receiver
Combined Deterministic and Random
Jitter Tolerance
JDR
0.55
UIPP
Measured at receiver
Total Jitter Tolerance
JT
0.65
UIPP
Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 14. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew
SMI
24
ns
Skew at the receiver input between lanes of a
multilane link
Bit Error Rate
BER
10–12
Unit Interval
UI
400
ps
±100 ppm
Table 39. Receiver AC Timing Specifications—3.125 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential Input Voltage
VIN
200
1600
mVPP
Measured at receiver
Deterministic Jitter Tolerance
JD
0.37
UIPP
Measured at receiver
Combined Deterministic and Random
Jitter Tolerance
JDR
0.55
UIPP
Measured at receiver
Total Jitter Tolerance
JT
0.65
UIPP
Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 14. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew
SMI
22
ns
Skew at the receiver input between lanes of a
multilane link
Table 37. Receiver AC Timing Specifications—1.25 GBaud (continued)
Characteristic
Symbol
Range
Unit
Notes
Min
Max
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSC8144EC 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core Digital Signal Processor
MSC8144ESVT1000B 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA BOX - Trays 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144ESVT800A 制造商:Freescale Semiconductor 功能描述:DSP 32BIT 800MHZ 800MIPS 783FCBGA - Trays
MSC8144ESVT800B 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 800MHZ 800MIPS 783-PIN FCBGA EACH - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144ETVT1000A 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA - Bulk
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