- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371135 > MPC9774 (Motorola, Inc.) 3.3V / 2,5V 1:14 LVCMOS PLL CLOCK GENERATOR PDF資料下載
參數(shù)資料
| 型號： | MPC9774 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 3.3V / 2,5V 1:14 LVCMOS PLL CLOCK GENERATOR |
| 中文描述： | 3.3 / 2,5 V 13:14:00的LVCMOS PLL時鐘發(fā)生器 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 217K |
| 代理商： | MPC9774 |
MPC9774
MOTOROLA
TIMING SOLUTIONS
8
APPLICATIONS INFORMATION
MPC9774 Configurations
Configuring the MPC9774 amounts to properly configuring
the internal dividers to produce the desired output
frequencies. The output frequency can be represented by
this formula:
÷
VCO_SEL
÷
M
÷
N
fREF
fOUT
fOUT = fREF
M
÷
N
PLL
where fREF is the reference frequency of the selected input
clock source (CCLKO or CCLK1), M is the PLL feedback
divider and N is a output divider. M is configured by the
FSEL_FB[0:1] and N is individually configured for each
output bank by the FSEL_A, FSEL_B and FSEL_C inputs.
The reference frequency fREF and the selection of the
feedback-divider M is limited by the specified VCO frequency
range. fREF and M must be configured to match the VCO
frequency range of 200 to 5001 MHz (VCC = 3.3V) in order to
achieve stable PLL operation:
fVCO,MIN
(fREF
VCO_SEL
M)
fVCO,MAX
The PLL post-divider VCO_SEL is either a divide-by-two
or a divide-by-four and can be used to situate the VCO into
the specified frequency range. This divider is controlled by
the VCO_SEL pin. VCO_SEL effectively extends the usable
input frequency range while it has no effect on the output to
reference frequency ratio. The output frequency for each
bank can be derived from the VCO frequency and the output
divider:
fQA[4:0] = fVCO
÷
(VCO_SEL
NA)
fQB[4:0] = fVCO
÷
(VCO_SEL
NB)
fQC[3:0] = fVCO
÷
(VCO_SEL
NC)
Table 11. MPC9774 Divider
Divider
Function
VCO_SEL
Values
M
PLL feedback
FSEL_FB[0:2]
÷
2
÷
4
÷
2
÷
4
÷
2
÷
4
÷
2
÷
4
8, 12, 16, 24
16, 24, 32, 48
NA
Bank A Output
Divider FSEL_A
4, 8
8, 16
NB
Bank B Output
Divider FSEL_B
4, 8
8, 16
NC
Bank C Output
Divider FSEL_C
8, 12
16, 24
1. The VCO frequency range for 2.5V operation is specified
from 200 to 400 MHz.
Table 11 shows the various PLL feedback and output
dividers. The output dividers for the three output banks allow
the user to configure the outputs into 1:1, 2:1, 3:2 and 3:2:1
frequency ratios. Figure 3 and Figure 4 display example
configurations for the MPC9774:
Figure 3. Example Configuration
Figure 4. Example Configuration
MPC9774
fref = 20.83 MHz
125 MHz
62.5 MHz
20.83 MHz (Feedback)
62.5 MHz
MPC9774 example configuration (feedback of
QFB = 20.83 MHz, VCO_SEL =
÷
2, M = 12, NA =
2, NB = 4, NC = 4, fVCO = 500 MHz).
Frequency range
Min
Max
Input
8.33 MHz
20.83 MHz
QA outputs
50 MHz
125 MHz
QB outputs
QC outputs
25 MHz
25 MHz
62.5 MHz
62.5 MHz
CCLK0
CCLK1
CCLK_SEL
VCO_SEL
FB_IN
FSEL_A
FSEL_B
FSEL_C
FSEL_FB[1:0]
QA[4:0]
QB[4:0]
QC[3:0]
QFB
0
0
1
0
10
MPC9774
fref = 25 MHz
100 MHz
50 MHz
25 MHz (Feedback)
33.3 MHz
MPC9774 example configuration (feedback of
QFB = 25 MHz, VCO_SEL =
÷
2, M = 8, NA = 2,
NB = 4, NC = 6, fVCO = 400 MHz).
Frequency range
Min
Max
Input
20 MHz
48 MHz
QA outputs
50 MHz
120 MHz
QB outputs
QC outputs
50 MHz
100 MHz
120 MHz
200 MHz
CCLK0
CCLK1
CCLK_SEL
VCO_SEL
FB_IN
FSEL_A
FSEL_B
FSEL_C
FSEL_FB[1:0]
QA[4:0]
QB[4:0]
QC[3:0]
QFB
0
0
1
1
01
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC980 | Dual 3.3V PLL Clock Generator(雙3.3V PLL時鐘發(fā)生器) |
| MPC9855 | Clock Generator for PowerQUICC and PowerPC Microprocessors |
| MPC992 | Low Voltage PLL Clock Driver(低壓PLL時鐘驅(qū)動器) |
| MPC993 | Dynamic Switch PLL Clock Driver(動態(tài)開關(guān)PLL時鐘驅(qū)動器) |
| MPC9990 | Low Voltage PLL Clock Driver(低壓PLL時鐘驅(qū)動器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9774AE | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9774AER2 | 功能描述:IC PLL CLK GEN 1:14 3.3V 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC9774FA | 功能描述:鎖相環(huán) - PLL 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9774FAR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC97H73AE | 功能描述:IC PLL CLK GEN 1:12 3.3V 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。