- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371135 > MPC993 (Motorola, Inc.) Dynamic Switch PLL Clock Driver(動態(tài)開關(guān)PLL時(shí)鐘驅(qū)動器) PDF資料下載
參數(shù)資料
| 型號： | MPC993 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dynamic Switch PLL Clock Driver(動態(tài)開關(guān)PLL時(shí)鐘驅(qū)動器) |
| 中文描述： | 動態(tài)開關(guān)PLL時(shí)鐘驅(qū)動器（動態(tài)開關(guān)鎖相環(huán)時(shí)鐘驅(qū)動器） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 97K |
| 代理商： | MPC993 |
SEMICONDUCTOR TECHNICAL DATA
1
REV 1
Motorola, Inc. 1999
07/99
The MPC993 is a PLL clock driver designed specifically for redundant
clock tree designs. The device receives two differential LVPECL clock
signals from which it generates 5 new differential LVPECL clock outputs.
Two of the output pairs regenerate the input signals frequency and phase
while the other three pairs generate 2x, phase aligned clock outputs.
External PLL feedback is used to also provide zero delay buffer
performance.
Fully Integrated PLL
Intelligent Dynamic Clock Switch
LVPECL Clock Outputs
LVCMOS Control/Statis I/O
3.3V Operation
32–Lead TQFP Packaging
±
50ps Cycle–Cycle Jitter
The MPC993 continuously monitors the two input signals to identify faulty reference clocks. Upon identification of a faulty
input clock (input clock stuck HIGH or LOW for at least 3 feedback clock edges), an input bad flag will be set and the device will
automatically switch from the bad reference clock input to the good one. During this dynamic switch of the input references, the
MPC993 outputs will slew, with minimal period disturbances to the new phase.
Figure 1. Block Diagram
CLK0
CLK0
CLK1
CLK1
Ext_FB
Ext_FB
OR
Sel_Clk
Dynamic Switch
Logic
PLL
PLL_En
÷
2
÷
4
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qa0
Qa0
Qa1
Qa1
MR
M
A
I
I
C
FA SUFFIX
32–LEAD PLASTIC TQFP PACKAGE
CASE 751D–04
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC9990 | Low Voltage PLL Clock Driver(低壓PLL時(shí)鐘驅(qū)動器) |
| MPF102 | JFET VHF Amplifier |
| MPF102 | JFET VHF Amplifier |
| MPF102 | N-Channel RF Amplifier |
| MPF4392 | JFETs Switching |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9992 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR |
| MPC9992AC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9992ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9992FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 400MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9992FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。