參數(shù)資料
型號(hào)： MPC9774
廠商： Motorola, Inc.
英文描述： 3.3V / 2,5V 1:14 LVCMOS PLL CLOCK GENERATOR
中文描述： 3.3 / 2,5 V 13:14:00的LVCMOS PLL時(shí)鐘發(fā)生器
文件頁(yè)數(shù)： 3/16頁(yè)
文件大?。?/td> 217K
代理商： MPC9774
MPC9774
TIMING SOLUTIONS
3
MOTOROLA
Table 1. PIN CONFIGURATION
Pin
I/O
Type
Function
CCLK0
CCLK1
FB_IN
CCLK_SEL
VCO_SEL
PLL_EN
MR/OE
CLK_STOP
FSEL_A
FSEL_B
FSEL_C
FSEL_FB[1:0]
QA[4:0]
QB[4:0]
QC[3:0]
QFB
GND
VCC_PLL
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Supply
Supply
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
VCC
PLL reference clock
Alternative PLL reference clock
PLL feedback signal input, connect to QFB
LVCMOS clock reference select
VCO operating frequency select
PLL enable/PLL bypass mode select
Output enable/disable (high-impedance tristate) and device reset
Output enable/clock stop (logic low state)
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
Frequency divider select for the QFB output
Clock outputs (Bank A)
Clock outputs (Bank B)
Clock outputs (Bank C)
PLL feedback output. Connect to FB_IN.
Negative power supply
PLL positive power supply (analog power supply). It is recommended to use an external RC filter
for the analog power supply pin VCC_PLL. Please see applications section for details.
Positive power supply for I/O and core. All VCC pins must be connected to the positive power
supply for correct operation
VCC
Supply
VCC
Table 2. Function Table (MPC9774 configuration controls)
Control
CCLK_SEL
VCO_SEL
Default
0
0
0
1
Selects CCLK0 as PLL refererence signal input
Selects VCO
÷
2. The VCO frequency is scaled by a
factor of 2 (high input frequency range)
Selects CCKL1 as PLL reference signal input
Selects VCO
÷
4. The VCO frequency is scaled by a
factor of 4 (low input frequency range).
PLL_EN
1
Test mode with the PLL bypassed. The reference clock is
substituted for the internal VCO output. MPC9774 is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
Normal operation mode with PLL enabled.
CLK_STOP
1
QA, QB an QC outputs disabled in logic low state. QFB
is not affected by CLK_STOP. CLK_STOP deassertion
may cause the initial output clock pulse to be distorted.
Outputs enabled (active)
MR/OE
1
Outputs disabled (high-impedance state) and reset of the
device. During reset/output disable the PLL feedback
loop is open and the internal VCO is tied to its lowest
frequency. The MPC9774 requires reset after any loss of
PLL lock. Loss of PLL lock may occur when the external
feedback path is interrupted. The length of the reset
pulse should be greater than one reference clock cycle
(CCLKx). The device is reset by the internal power–on
reset (POR) circuitry during power–up.
VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios.
See
Table 3
and
Table 4
for the device frequency configuration.
Outputs enabled (active)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC9774AE 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MPC9774AER2 功能描述:IC PLL CLK GEN 1:14 3.3V 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
MPC9774FA 功能描述:鎖相環(huán) - PLL 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
MPC9774FAR2 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MPC97H73AE 功能描述:IC PLL CLK GEN 1:12 3.3V 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
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