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參數(shù)資料
| 型號： | MPC9990 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Voltage PLL Clock Driver(低壓PLL時鐘驅(qū)動器) |
| 中文描述： | 低電壓PLL時鐘驅(qū)動器（低壓鎖相環(huán)時鐘驅(qū)動器） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 143K |
| 代理商： | MPC9990 |
SEMICONDUCTOR TECHNICAL DATA
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Motorola, Inc. 2000
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The MPC9990 is a low voltage PLL clock driver designed for high
speed clock generation and distribution in high performance computer,
workstation and server applications. The clock driver accepts a LVPECL
compatible clock signal and provides 10 low skew, differential HSTL1
compatible outputs, one HSTL compatible output for system
synchronization purpose and one PECL compatible PLL feedback output.
The device operates from a dual voltage supply: 3.3V for the core logic
and 1.8V for the HSTL outputs. The fully integrated PLL supports an input
frequency range of 150 to 300 MHz. The output frequencies are
configurable.
Supports high performance HSTL clock distribution systems
Compatible to IA64 processor systems
Fully Integrated PLL, differential design
External feedback enables zero–delay buffer designs
Core logic operates from 3.3V power supply
HSTL outputs operate from a 1.8V supply
Programmable frequency by output bank
10 HSTL compatible outputs (two banks)
PECL compatible PLL feedback output
HSTL compatible SYNC output
Guaranteed max. low skew of 50 ps within device
Guaranteed max. low skew of 200 ps part–to–part
LVPECL compatible clock input, LVCMOS compatible control inputs
Temperature range of 0 to +70 deg C
The MPC9990 provides output clock frequencies required for high–performance computer system optimization. The device
drives up to 10 differential clock loads within the frequency range of 150 to 300 MHz. The 10 outputs are organized in 2 banks of 5
differential outputs. In the standard configuration the QFB output pair is connected to the FB input pair closing the PLL loop and
enabling zero delay operation from the CLK input to the outputs. Bank B outputs are frequency and phase aligned to the CLK
input, providing exact copies of the high–speed input signal. Bank A outputs are configured to operate at slower speeds driving
the system bus devices. The output frequency ratio of bank A to bank B is adjustable (for available ratios, see ”MPC9990
Application: CPU to System Bus Frequency Ratios” on page 2) for system optimization. In a computer application, bank B
outputs generate the clock signals for the devices operating at the CPU frequency, while Bank A outputs are configured to drive
the clock signals for the devices running at lower speeds (system clock). 8 individual frequency ratios are available, providing a
high degree of flexibility. The frequency ratios between CPU clock and system clock provided by the MPC9990 are listed in the
table ”output configuration” on page 4.
The SYNC output functionality is designed for system synchronization purpose. The SYNC output is asserted at coincident
rising edges of CPU (bank B and CLK input signal) and slower system clock (bank A) outputs (see ”SYNC Phase Relation
Diagram” on page 4), providing baseline timing in systems with fractional clocks. The SYNC output is asserted for one QB high
pulse, centered on the rising QBx output.
Figure 1. MPC9990 Example Application
MPC990
250 MHz
QFB
FB
SYNC
QB[0:4]
CLK
QA[0:4]
250 MHz
250 MHz CPU clocks
Systemclocks: 250, 222, 219,
214, 208, 200, 187, 125 MHz
Systemsynchronization
1. In order to minimize output–to–output skew, HSTL outputs of the MPC9990 are generated with an open emitter architecture. For output
termination, see ”HSTL Output Termination and AC Test Reference” on page 6.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
LOW VOLTAGE
DIFFERENTIAL PECL–HSTL
PLL CLOCK DRIVER
FA SUFFIX
48–LEAD LQFP PACKAGE
CASE 932–03
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9992 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR |
| MPC9992AC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9992ACR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9992FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 400MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9992FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
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