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參數(shù)資料
| 型號： | MPC973 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE PLL CLOCK DRIVER |
| 中文描述： | 低壓PLL時鐘驅(qū)動器 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 182K |
| 代理商： | MPC973 |
MPC972 MPC973
MOTOROLA
TIMING SOLUTIONS
BR1333 — Rev 6
12
control of the MPC972/973 allows designers, under software
control, to implement unique power management schemes
into their designs. Although useful, individual output control
at the expense of one pin per output is too high, therefore a
simple serial interface was derived to economize on the
control pins.
The freeze control logic provides a mechanism through
which the MPC972 clock outputs may be frozen (stopped in
the logic ‘0’ state):
The freeze mechanism allows serial loading of the 12–bit
Serial Input Register, this register contains one program–
mable freeze enable bit for 12 of the 14 output clocks. The
Qc0 and QFB outputs cannot be frozen with the serial port,
this avoids any potential lock up situation should an error
occur in the loading of the Serial Input Register. The user
may programmably freeze an output clock by writing logic ‘0’
to the respective freeze enable bit. Likewise, the user may
programmably unfreeze an output clock by writing logic ‘1’ to
the respective enable bit.
The freeze logic will never force a newly–frozen clock to a
logic ‘0’ state before the time at which it would normally
transition there. The logic simply keeps the frozen clock at
logic ‘0’ once it is there. Likewise, the freeze logic will never
force a newly–unfrozen clock to a logic ‘1’ state before the
time at which it would normally transition there. The logic
re–enables the unfrozen clock during the time when the
respective clock would normally be in a logic ‘0’ state,
eliminating the possibility of ‘runt’ clock pulses.
The user may write to the Serial Input register through the
Frz_Data input by supplying a logic ‘0’ start bit followed
serially by 12 NRZ freeze enable bits. The period of each
Frz_Data bit equals the period of the free–running Frz_Clk
signal. The Frz_Data serial transmission should be timed so
the MPC972 can sample each Frz_Data bit with the rising
edge of the free–running Frz_Clk signal.
Figure 16. Freeze Data Input Protocol
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D0
Start
Bit
D0–D3 are the control bits for Qa0–Qa3, respectively
D4–D7 are the control bits for Qb0–Qb3, respectively
D8–D10 are the control bits for Qc1–Qc3, respectively
D11 is the control bit for QSync
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| MPC980 | Dual 3.3V PLL Clock Generator(雙3.3V PLL時鐘發(fā)生器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC974 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC974A44 F44A WAF | 制造商:Motorola Inc 功能描述: |
| MPC9772 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V 1:12 LVCMOS PLL Clock Generator |
| MPC9772AE | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9772AER2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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