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參數(shù)資料
| 型號： | MPC8323ECZQAFDC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 34/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PWRQUICC II 516-PBGA |
| 產(chǎn)品培訓模塊： | MPC8323E PowerQUICC II Pro Processor |
| 標準包裝： | 40 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 333MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 516-BBGA |
| 供應商設備封裝： | 516-FPBGA（27x27） |
| 包裝： | 托盤 |
| 配用： | MPC8323E-RDB-ND - BOARD REFERENCE DESIGN |
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
4
Freescale Semiconductor
Overview
1.1.2
Serial Interfaces
The MPC8323E serial interfaces are as follows:
Support for one UL2 interface with 31 multi-PHY addresses (MPC8323E and MPC8323 only)
Support for up to three 10/100 Mbps Ethernet interfaces using MII or RMII
Support for up to four T1/E1/J1/E3 or DS-3 serial interfaces (TDM)
Support for dual UART and SPI interfaces and a single I2C interface
1.2
QUICC Engine Block
The QUICC Engine block is a versatile communications complex that integrates several communications
peripheral controllers. It provides on-chip system design for a variety of applications, particularly in
communications and networking systems. The QUICC Engine block has the following features:
One 32-bit RISC controller for flexible support of the communications peripherals
Serial DMA channel for receive and transmit on all serial channels
Five universal communication controllers (UCCs) supporting the following protocols and
interfaces (not all of them simultaneously):
— 10/100 Mbps Ethernet/IEEE 802.3 standard
— IP support for IPv4 and IPv6 packets including TOS, TTL, and header checksum processing
— ATM protocol through UTOPIA interface (note that the MPC8321 and MPC8321E do not
support the UTOPIA interface)
— HDLC /transparent up to 70-Mbps full-duplex
— HDLC bus up to 10 Mbps
— Asynchronous HDLC
— UART
— BISYNC up to 2 Mbps
— QUICC multi-channel controller (QMC) for 64 TDM channels
One UTOPIA interface (UPC1) supporting 31 multi-PHYs (MPC8323E- and MPC8323-specific)
Two serial peripheral interfaces (SPI). SPI2 is dedicated to Ethernet PHY management.
Four TDM interfaces
Thirteen independent baud rate generators and 19 input clock pins for supplying clocks to UCC
serial channels
Four independent 16-bit timers that can be interconnected as two 32-bit timers
The UCCs are similar to the PowerQUICC II peripherals: SCC (BISYNC, UART, and HDLC bus) and
FCC (fast Ethernet, HDLC, transparent, and ATM).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8323ECZQAFDCA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications |
| MPC8323EEC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications |
| MPC8323E-MDS-PB | 功能描述:開發(fā)板和工具包 - 其他處理器 MPC8323E PROCESSOR BOARD RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8323E-RDB | 功能描述:開發(fā)板和工具包 - 其他處理器 REFERENCE DESIGN PQII PR RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8323E-RDB | 制造商:Freescale Semiconductor 功能描述:MPC8323E Integrated Multiservice Gateway |
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