參數(shù)資料
型號(hào)： MPC8323ECZQAFDC
廠商： Freescale Semiconductor
文件頁數(shù)： 16/82頁
文件大?。?/td> 0K
描述： IC MPU PWRQUICC II 516-PBGA
產(chǎn)品培訓(xùn)模塊： MPC8323E PowerQUICC II Pro Processor
標(biāo)準(zhǔn)包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 333MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應(yīng)商設(shè)備封裝： 516-FPBGA（27x27）
包裝： 托盤
配用： MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Freescale Semiconductor
23
Ethernet and MII Management
8.2.2.1
RMII Transmit AC Timing Specifications
Table 23 provides the RMII transmit AC timing specifications.
Figure 10 shows the RMII transmit AC timing diagram.
Figure 10. RMII Transmit AC Timing Diagram
8.2.2.2
RMII Receive AC Timing Specifications
Table 24 provides the RMII receive AC timing specifications.
Table 25. RMII Transmit AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
REF_CLK clock
tRMX
—20
—
ns
REF_CLK duty cycle
tRMXH/tRMX
35
—
65
%
REF_CLK to RMII data TXD[1:0], TX_EN delay
tRMTKHDX
2
—
10
ns
REF_CLK data clock rise VIL(min) to VIH(max)
tRMXR
1.0
—
4.0
ns
REF_CLK data clock fall VIH(max) to VIL(min)
tRMXF
1.0
—
4.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX symbolizes RMII
transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
Table 26. RMII Receive AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
REF_CLK clock period
tRMX
—20
—
ns
REF_CLK duty cycle
tRMXH/tRMX
35
—
65
%
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
tRMRDVKH
4.0
—
ns
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
tRMRDXKH
2.0
—
ns
REF_CLK clock rise VIL(min) to VIH(max)
tRMXR
1.0
—
4.0
ns
REF_CLK
TXD[1:0]
tRMTKHDX
tRMX
tRMXH
tRMXR
tRMXF
TX_EN
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