參數(shù)資料
型號： MPC8323ECZQAFDC
廠商： Freescale Semiconductor
文件頁數(shù)： 18/82頁
文件大?。?/td> 0K
描述： IC MPU PWRQUICC II 516-PBGA
產(chǎn)品培訓模塊： MPC8323E PowerQUICC II Pro Processor
標準包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 333MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應商設備封裝： 516-FPBGA（27x27）
包裝： 托盤
配用： MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Freescale Semiconductor
25
Ethernet and MII Management
8.3.1
MII Management DC Electrical Characteristics
MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for
MDIO and MDC are provided in Table 27.
8.3.2
MII Management AC Electrical Specifications
Table 28 provides the MII management AC timing specifications.
Table 27. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage (3.3 V)
OVDD
—
2.97
3.63
V
Output high voltage
VOH
IOH = –1.0 mA
OVDD = Min
2.10
OVDD + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
OVDD = Min
GND
0.50
V
Input high voltage
VIH
—2.00
—
V
Input low voltage
VIL
——
0.80
V
Input current
IIN
0 V
≤ VIN ≤ OVDD
—±5
μA
Table 28. MII Management AC Timing Specifications
At recommended operating conditions with OVDD is 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
Notes
MDC frequency
fMDC
—2.5
—
MHz
—
MDC period
tMDC
—400
—
ns
—
MDC clock pulse width high
tMDCH
32
—
ns
—
MDC to MDIO delay
tMDKHDX
10
—
70
ns
—
MDIO to MDC setup time
tMDDVKH
5—
—
ns
—
MDIO to MDC hold time
tMDDXKH
0—
—
ns
—
MDC rise time
tMDCR
—
10
ns
—
MDC fall time
tMDHF
—
10
ns
—
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
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相關代理商/技術參數(shù)
參數(shù)描述
MPC8323ECZQAFDCA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications
MPC8323EEC 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications
MPC8323E-MDS-PB 功能描述:開發(fā)板和工具包 - 其他處理器 MPC8323E PROCESSOR BOARD RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MPC8323E-RDB 功能描述:開發(fā)板和工具包 - 其他處理器 REFERENCE DESIGN PQII PR RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MPC8323E-RDB 制造商:Freescale Semiconductor 功能描述:MPC8323E Integrated Multiservice Gateway
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