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| 型號： | MPC8245LZU300X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352 |
| 文件頁數(shù)： | 41/60頁 |
| 文件大小： | 620K |
| 代理商： | MPC8245LZU300X |
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46
MPC8245 Integrated Processor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
Voltage sequencing requirements for the MPC8245 are similar to those for the MPC8240; however, there
are two changes which are applicable for the MPC8245. First, there is an additional requirement for the
MPC8245 that the non-PCI input voltages (VIN) must not be greater than either GVdd or OVdd by more
than 0.6 V at all times including during power-on reset (see Caution 5 of Table 2). Second, for the
MPC8245, LVdd must not exceed OVdd by more than 3.0 V at any time including during power-on reset
(see Caution 10 of Table 2); the allowable separation between LVdd and OVdd is 3.6 V for the MPC8240.
There is no LAVdd input voltage supply signal on the MPC8245 since the SDRAM clock delay-locked
loop (DLL) has power supplied internally. Signal D17 should be treated as a no-connect for the MPC8245.
1.7.9 JTAG Conguration Signals
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the MPC8245
are available from Motorola or Distributor Sales/FAE Representatives) The TRST signal is optional in the
IEEE 1149.1 specication but is provided on all PowerPC implementations. While it is possible to force
the TAP controller to the reset state using only the TCK and TMS signals, PowerPC implementations
require the TRST signal to be asserted during reset. Since the JTAG interface is also used for accessing the
common on-chip processor (COP) function of PowerPC processors, simply tying TRST to
HRST_CPU/HRST_CTRL is not practical. Note that the two hard reset signals on the MPC8245
(HRST_CPU and HRST_CTRL) must be asserted and negated together to guarantee normal operation.
The common on-chip processor (COP) function of PowerPC processors allows a remote computer system
(typically a PC with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The COP interface connects primarily through the JTAG port of the processor,
with some additional status monitoring signals. The COP port requires the ability to independently assert
HRST_CPU/HRST_CTRL or TRST in order to fully control the processor. If the target system has
independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, then the COP reset signals must be merged into these signals with logic.
The arrangement shown in Figure 28 allows the COP to independently assert HRST_CPU/HRST_CTRL
or TRST while insuring that the target can drive HRST_CPU/HRST_CTRL as well. The COP header
shown
adds
many
benets
including
breakpoints,
watchpoints,
register
and
memory
examination/modication and other standard debugger features are possible through this interface.
Availability of these features can be as inexpensive as an unpopulated footprint for a header to be added
when needed. The CHKSTOP_IN signal access can be utilized by external test equipment to signal a check
stop to the MPC8245. Note the CHKSTOP_IN and SRESET signals are not available in the Extended
ROM Mode.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post 0.100" centered header assembly (often called a “Berg” header). The connector typically has
pin 14 removed as a connector key, as shown in Figure 28.
There is no standardized way to number the COP header shown in Figure 28; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin one (as with an IC). Regardless of the numbering, the signal placement recommended
in Figure 28 is common to all known emulators.
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