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參數(shù)資料
| 型號： | MPC8245LZU300X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352 |
| 文件頁數(shù)： | 38/60頁 |
| 文件大?。?/td> | 620K |
| 代理商： | MPC8245LZU300X |
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MPC8245 Integrated Processor Hardware Specications
43
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
Figure 27. Example LVdd and OVdd Voltage Sequencing Circuits
1.7.3 Power Supply Sizing
The power consumption numbers provided in Table 5 do not reect power from the OVdd and GVdd
power supplies which are non-negligible for the MPC8245. In typical application measurements, the OVdd
power ranged from 200 to 600 mW and the GVdd power ranged from 300 to 900 mW. The ranges’ low end
power numbers were results of the MPC8245 performing cache resident integer operations at the slowest
frequency combination of 33:66:200 (PCI:Mem:CPU) MHz. The OVdd high end range’s value resulted
from the MPC8245 operating at the fastest frequency combination of 66:100:300 (PCI:Mem:CPU) MHz
and performing continuous ushes of cache lines with alternating ones and zeroes to PCI memory. The
GVdd high end range’s value resulted from the MPC8245 operating at the fastest frequency combination
of 66:100:300 (PCI:Mem:CPU) MHz and performing continuous ushes of cache lines with alternating
ones and zeroes on 64 bit boundaries to local memory.
1.7.4 Decoupling Recommendations
Due to its dynamic power management feature, the large address and data buses, and its high operating
frequencies, the MPC8245 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC8245 system, and the MPC8245 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at
each Vdd, OVdd, GVdd, and LVdd pin of the MPC8245. It is also recommended that these decoupling
capacitors receive their power from separate Vdd, OVdd, GVdd, and GND power planes in the PCB,
utilizing short traces to minimize inductance. These capacitors should have a value of 0.1 F. Only ceramic
SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508
or 0603, oriented such that connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the Vdd, OVdd, GVdd, and LVdd planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS tantalum or Sanyo OSCON).
1.7.5 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVdd. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external Vdd, OVdd, GVdd, LVdd and GND pins of the
MPC8245.
MUR420
+3.3V OVdd
3.3V
Source
+3.3V LVdd
Source
3.3V
MUR420
+3.3V OVdd
3.3V
Source
+5.0V LVdd
Source
5.0V
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