參數(shù)資料
型號: MPC8245LZU300X
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件頁數(shù): 33/60頁
文件大?。?/td> 620K
代理商: MPC8245LZU300X
MPC8245 Integrated Processor Hardware Specications
39
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
PLL Conguration
Notes:
1
Limited by maximum PCI input frequency (66 MHz).
2
Limited by maximum system memory interface operating frequency (100 MHz @ 300 MHz CPU).
3
Limited by minimum memory VCO frequency. (132 MHz)
4
Limited due to maximum memory VCO frequency. (336 MHz)
5
Limited by maximum CPU operating frequency.
6
Limited by minimum CPU VCO frequency. (200 MHz)
7
Limited by maximum CPU VCO frequency. (See Table 7)
8
In Clock Off mode, no clocking occurs inside the MPC8245 regardless of the PCI_SYNC_IN input.
9
Range values are shown rounded down to the nearest whole number (decimal place accuracy removed)
for clarity.
10 PLL_CFG[0–4] settings not listed (01011, 01101, 01111, 10001, 10011, 10101, 11001, and 11011) are
reserved.
11 Multiplier ratios for this PLL_CFG[0–4] setting are different from the MPC8240 and are not backwards
compatible.
12 PCI_SYNC_IN range for this PLL_CFG[0–4] setting is different from the MPC8240 and may not be fully
backwards compatible.
13 Bits 7– 4 of register offset <0xE2> contain the PLL_CFG[0–4] setting value.
14 In PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral
logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended
for hardware modeling support. The AC timing specications given in this document do not apply in PLL
Bypass mode.
15 In Dual PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the
peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation.
In this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode
operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be
externally synchronized. This mode is intended for hardware modeling support. The AC timing specica-
tions given in this document do not apply in Dual PLL Bypass mode.
16 Limited by maximum system memory interface operating frequency (133 MHz @ 266 MHz CPU).
17 Limited by minimum CPU operating frequency.
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