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參數(shù)資料
| 型號： | MPC8245LZU300X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352 |
| 文件頁數(shù)： | 36/60頁 |
| 文件大小： | 620K |
| 代理商： | MPC8245LZU300X |
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MPC8245 Integrated Processor Hardware Specications
41
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
3
Limited by minimum memory VCO frequency. (132 MHz)
4
Limited due to maximum memory VCO frequency. (336 MHz)
5
Limited by maximum CPU operating frequency.
6
Limited by minimum CPU VCO frequency. (200 MHz)
7
Limited by maximum CPU VCO frequency. (See Table 7)
8
In Clock Off mode, no clocking occurs inside the MPC8245 regardless of the PCI_SYNC_IN input.
9
Range values are shown rounded down to the nearest whole number (decimal place accuracy removed)
for clarity.
10 PLL_CFG[0–4] settings not listed ( 01111, 10001, 10011, 10111, and 11011) are reserved.
11 Multiplier ratios for this PLL_CFG[0–4] setting are different from the MPC8240 and are not backwards
compatible.
12 PCI_SYNC_IN range for this PLL_CFG[0–4] setting is different from the MPC8240 and may not be fully
backwards compatible.
13 Bits 7– 4 of register offset <0xE2> contain the PLL_CFG[0–4] setting value.
14 In PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral
logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended
for hardware modeling support. The AC timing specications given in this document do not apply in PLL
Bypass mode.
15 In Dual PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the
peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation.
In this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode
operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be
externally synchronized. This mode is intended for hardware modeling support. The AC timing specica-
tions given in this document do not apply in Dual PLL Bypass mode.
16 Limited by maximum system memory interface operating frequency (133 MHz @ Vdd/AVdd/AVdd2 = 2.0
V ±100 mV).
17 Limited by minimum CPU operating frequency.
1.7 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8245.
1.7.1 PLL Power Supply Filtering
The AVdd and AVdd2 power signals are provided on the MPC8245 to provide power to the peripheral
logic/memory bus PLL and the 603e processor PLL. To ensure stability of the internal clocks, the power
supplied to the AVdd and AVdd2 input signals should be ltered of any noise in the 500kHz to 10MHz
resonant frequency range of the PLLs. Two separate circuits similar to the one shown in Figure 25 using
surface mount capacitors with minimum effective series inductance (ESL) is recommended for AVdd and
AVdd2 power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High Speed
Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal
value are recommended over using multiple values.
The circuits should be placed as close as possible to the respective input signal pins to minimize noise
coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with
minimal inductance of vias is important.
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