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參數(shù)資料
| 型號： | MPC8245LZU300X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352 |
| 文件頁數(shù)： | 13/60頁 |
| 文件大?。?/td> | 620K |
| 代理商： | MPC8245LZU300X |
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20
MPC8245 Integrated Processor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.3.2 Input AC Timing Specications
Notes:
1
All memory and related interface input signal specications are measured from the TTL level (0.8 or 2.0
V) of the signal in question to the VM = 1.4 V of the rising edge of the memory bus clock,
SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the fre-
quency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of
PCI_SYNC_IN). See Figure 9.
2
All PCI signals are measured from OVdd/2 of the rising edge of PCI_SYNC_IN to 0.4*OVdd of the sig-
nal in question for 3.3 V PCI signaling levels. See Figure 10.
3
Input timings are measured at the pin.
4tCLK is the time of one SDRAM_SYNC_IN clock cycle.
5
All mode select input signals specications are measured from the TTL level (0.8 or 2.0 V) of the signal in
6
The memory interface input setup and hold times are programmable to four possible combinations by
programming bits 5:4 of Register Offset <0x77> to select the desired input setup and hold times.
7Tos represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the inter-
nal delay present on the SDRAM_SYNC_IN signal with respect to the sys_logic_clk inputs to the DLL,
the resulting SDRAM clocks become offset by the delay amount. The feedback trace length of
SDRAM_SYNC_OUT to SDRAM_SYNC_IN must be shortened by this amount relative to the SDRAM
clock output trace lengths to maintain phase alignment of the memory clocks with respect to
sys_logic_clk.
Table 9. Input AC Timing Specifications
At recommended operating conditions (see Table 2.) with LVdd = 3.3 V ± 0.3V
Num
Characteristic
Min
Max
Units
Notes
10a
PCI Input Signals Valid to PCI_SYNC_IN (Input Setup)
3.0
—
ns
2,3
10b
Memory Input Signals Valid to SDRAM_SYNC_IN (Input Setup)
10b0 Tap 0, Register Offset <0x77>, bits 5:4 = 0b10
2.6
—
ns
1,3,6
10b1 Tap 1, Register Offset <0x77>, bits 5:4 = 0b11
1.9
—
10b2 Tap 2, Register Offset <0x77>, bits 5:4 = 0b00 (Default)
1.2
—
10b3 Tap 3, Register Offset <0x77>, bits 5:4 = 0b01
0.5
—
10c
Epic, Misc. Debug Input Signals Valid to SDRAM_SYNC_IN
(Input Setup)
3.0
—
ns
1,3
10d
I2C Input Signals Valid to SDRAM_SYNC_IN (Input Setup)
3.0
—
ns
1,3
10e
Mode select Inputs Valid to HRST_CPU / HRST_CTRL (Input Setup)
9*tCLK
—
ns
1,3–5
11
Tos - SDRAM_SYNC_IN to sys_logic_clk offset time
0.65
1.0
ns
7
11a
SDRAM_SYNC_IN to Memory Signal Inputs Invalid (Input Hold)
11a0 Tap 0, Register Offset <0x77>, bits 5:4 = 0b10
0
—
ns
1,3,6
11a1 Tap 1, Register Offset <0x77>, bits 5:4 = 0b11
0.7
—
11a2 Tap 2, Register Offset <0x77>, bits 5:4 = 0b00 (Default)
1.4
—
11a3 Tap 3, Register Offset <0x77>, bits 5:4 = 0b01
2.1
—
11b
HRST_CPU / HRST_CTRL to Mode Select Inputs Invalid (Input Hold)
0
—
ns
1,3,5
11c
PCI_SYNC_IN to Inputs Invalid (Input Hold)
1.0
—
ns
1,2,3
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