參數(shù)資料
型號： MPC750
廠商： Motorola, Inc.
英文描述： Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes
中文描述： MPC750 RISC微處理器
文件頁數(shù)： 9/31頁
文件大?。?/td> 318K
代理商： MPC750
MPC750 RISC Microprocessor Technical Summary
9
Each IU consists of three single-cycle subunits—a fast adder/comparator, a subunit for logical operations,
and a subunit for performing rotates, shifts, and count-leading-zero operations. These subunits handle all
one-cycle arithmetic instructions; only one subunit can execute an instruction at a time.
The IU1 has a 32-bit integer multiplier/divider as well as the adder, shift, and logical units of the IU2. The
multiplier supports early exit for operations that do not require full 32-
x
32-bit multiplication.
Each IU has a dedicated result bus (not shown in Figure 1) that connects to rename buffers.
1.1.2.4.2 Floating-Point Unit (FPU)
The FPU, shown in Figure 1, is designed such that single-precision operations require only a single pass,
with a latency of three cycles. As instructions are dispatched to the FPU’s reservation station, source operand
data can be accessed from the FPRs or from the FPR rename buffers. Results in turn are written to the
rename buffers and are made available to subsequent instructions. Instructions pass through the reservation
station in dispatch order.
The FPU contains a single-precision multiply-add array and the floating-point status and control register
(FPSCR). The multiply-add array allows the MPC750 to efficiently implement multiply and multiply-add
operations. The FPU is pipelined so that one single- or double-precision instruction can be issued per clock
cycle. Thirty-two 64-bit floating-point registers are provided to support floating-point operations. Stalls due
to contention for FPRs are minimized by automatic allocation of the six floating-point rename registers. The
MPC750 writes the contents of the rename registers to the appropriate FPR when floating-point instructions
are retired by the completion unit.
The MPC750 supports all IEEE 754 floating-point data types (normalized, denormalized, NaN, zero, and
infinity) in hardware, eliminating the latency incurred by software exception routines. (Note that exception
is also referred to as interrupt in the architecture specification.)
1.1.2.4.3 Load/Store Unit (LSU)
The LSU executes all load and store instructions and provides the data transfer interface between the GPRs,
FPRs, and the cache/memory subsystem. The LSU calculates effective addresses, performs data alignment,
and provides sequencing for load/store string and multiple instructions.
Load and store instructions are issued and translated in program order; however, some memory accesses can
occur out of order. Synchronizing instructions can be used to enforce strict ordering. When there are no data
dependencies and the guarded bit for the page or block is cleared, a maximum of one out-of-order cacheable
load operation can execute per cycle, with a two-cycle total latency on a cache hit. Data returned from the
cache is held in a rename register until the completion logic commits the value to a GPR or FPR. Stores
cannot be executed out of order and are held in the store queue until the completion logic signals that the
store operation is to be completed to memory. The MPC750 executes store instructions with a maximum
throughput of one per cycle and a three-cycle total latency to the data cache. The time required to perform
the actual load or store operation depends on the processor/bus clock ratio and whether the operation
involves the on-chip cache, the L2 cache, system memory, or an I/O device.
1.1.2.4.4 System Register Unit (SRU)
The SRU executes various system-level instructions, as well as condition register logical operations and
move to/from special-purpose register instructions. To maintain system state, most instructions executed by
the SRU are execution-serialized; that is, the instruction is held for execution in the SRU until all previously
issued instructions have executed. Results from execution-serialized instructions executed by the SRU are
not available or forwarded for subsequent instructions until the instruction completes.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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