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參數(shù)資料
| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數(shù)： | 15/31頁 |
| 文件大?。?/td> | 318K |
| 代理商： | MPC750 |
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MPC750 RISC Microprocessor Technical Summary
15
Figure 4. MPC750 Microprocessor Signal Groups
1.1.9 Clocking
The MPC750 requires a single system clock input, SYSCLK, that represents the bus interface frequency.
Internally, the processor uses a phase-locked loop (PLL) circuit to generate a master core clock that is
frequency-multiplied and phase-locked to the SYSCLK input. This core frequency is used to operate the
internal circuitry.
Data
Arbitration
L2 Cache
Address/
Data
BR
BG
ABB
TS
AP[0–3]
GBL
TSIZ[0–2]
AACK
ARTRY
SYSCLK
PLL_CFG[0–3]
DBG
DBWO
DBB
D[0–63]
DP[0–7]
TA
DRTRY
TEA
INT
JTAG/COP
Factory Test
1
1
1
1
1
5
3
4
TBST
WT
TT[0–4]
5
1
4
TBEN
1
CLK_OUT
MCP
SRESET
TLBISYNC
QREQ
L2ADDR[16–0]
SMI
HRESET
CKSTP_IN
QACK
CKSTP_OUT
L2DATA[0–63]
L2DP[0–7]
L2CE
L2WE
L2CLK_OUT[A–B]
3
1
1
1
1
1
1
1
8
64
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CI
1
A[0–31]
32
L2SYNC_OUT
Address
Arbitration
Address
Bus
L2SYNC_IN
L2ZZ
L2 Cache
Clock/
Control
Address
Termination
Address
Start
Transfer
Attributes
Data
Transfer
Data
Termination
Interrupts/
Resets
Processor
Status/
Control
V
DD
V
DD
(I/O)
Clock
Control
Test
Interface
RSRV
17
2
1
1
1
64
8
1
1
Not supported in the MPC740
L2V
DD
L2AV
DD
MPC750
DBDIS
1
AV
DD
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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