參數(shù)資料
型號(hào)： MPC750
廠商： Motorola, Inc.
英文描述： Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes
中文描述： MPC750 RISC微處理器
文件頁(yè)數(shù)： 7/31頁(yè)
文件大?。?/td> 318K
代理商： MPC750
MPC750 RISC Microprocessor Technical Summary
7
— Thermal management facility provides software-controllable thermal management. Thermal
management is performed through the use of three supervisor-level registers and an MPC750-
specific thermal management exception.
— Instruction cache throttling provides control of instruction fetching to limit power consumption.
Performance monitor can be used to help debug system designs and improve software efficiency.
In-system testability and debugging features through JTAG boundary-scan capability
Freescale Semiconductor, Inc.
1.1.2 Instruction Flow
As shown in Figure 1, the MPC750 instruction unit provides centralized control of instruction flow to the
execution units. The instruction unit contains a sequential fetcher, six-entry instruction queue (IQ), dispatch
unit, and BPU. It determines the address of the next instruction to be fetched based on information from the
sequential fetcher and from the BPU.
The sequential fetcher loads instructions from the instruction cache into the instruction queue. The BPU
extracts branch instructions from the sequential fetcher. Branch instructions that cannot be resolved
immediately are predicted using either the MPC750-specific dynamic branch prediction or the architecture-
defined static branch prediction.
Branch instructions that do not affect the LR or CTR are removed from the instruction stream. The BPU
folds branch instructions when a branch is taken (or predicted as taken); branch instructions that are not
taken, or predicted as not taken, are removed from the instruction stream through the dispatch mechanism.
Instructions issued beyond a predicted branch do not complete execution until the branch is resolved,
preserving the programming model of sequential execution. If branch prediction is incorrect, the instruction
unit flushes all predicted path instructions, and instructions are fetched from the correct path.
1.1.2.1 Instruction Queue and Dispatch Unit
The instruction queue (IQ), shown in Figure 1, holds as many as six instructions and loads up to four
instructions from the instruction cache during a single processor clock cycle. The instruction fetcher
continuously attempts to load as many instructions as there were vacancies in the IQ in the previous clock
cycle. All instructions except branch instructions are dispatched to their respective execution units from the
bottom two positions in the instruction queue (IQ0 and IQ1) at a maximum rate of two instructions per cycle.
Reservation stations are provided for the IU1, IU2, FPU, LSU, and SRU. The dispatch unit checks for source
and destination register dependencies, determines whether a position is available in the completion queue,
and inhibits subsequent instruction dispatching as required.
Branch instructions can be detected, decoded, and predicted from anywhere in the instruction queue. For a
more detailed discussion of instruction dispatch, see Section 2.6, “Instruction Timing.”
1.1.2.2 Branch Processing Unit (BPU)
The BPU receives branch instructions from the sequential fetcher and performs CR lookahead operations
on conditional branches to resolve them early, achieving the effect of a zero-cycle branch in many cases.
Unconditional branch instructions and conditional branch instructions in which the condition is known can
be resolved immediately. For unresolved conditional branch instructions, the branch path is predicted using
either the architecture-defined static branch prediction or the MPC750-specific dynamic branch prediction.
Dynamic branch prediction is enabled if HID0[BHT] = 1.
When a prediction is made, instruction fetching, dispatching, and execution continue from the predicted
path, but instructions cannot complete and write back results to architected registers until the prediction is
determined to be correct (resolved). When a prediction is incorrect, the instructions from the incorrect path
are flushed from the processor and processing begins from the correct path. The MPC750 allows a second
F
For More Information On This Product,
Go to: www.freescale.com
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