參數(shù)資料
型號(hào)： MPC750
廠商： Motorola, Inc.
英文描述： Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes
中文描述： MPC750 RISC微處理器
文件頁數(shù)： 14/31頁
文件大?。?/td> 318K
代理商： MPC750
14
MPC750 RISC Microprocessor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
Data termination signals—Data termination signals are required after each data beat in a data
transfer. In a single-beat transaction, a data termination signal also indicates the end of the tenure;
in burst accesses, data termination signals apply to individual beats and indicate the end of the
tenure only after the final data beat. They also indicate whether a condition exists that requires the
data phase to be repeated.
L2 cache clock/control signals—These signals provide clocking and control for the L2 cache. (The
L2 cache feature is not supported in the MPC740.)
L2 cache address/data—The MPC750 has separate address and data buses for accessing the L2
cache. (The L2 cache feature is not supported in the MPC740.)
Interrupt signals—These signals include the interrupt signal, checkstop signals, and both soft reset
and hard reset signals. These signals are used to generate interrupt exceptions and, under various
conditions, to reset the processor.
Processor status/control signals—These signals are used to set the reservation coherency bit, enable
the time base, and other functions.
Miscellaneous signals—These signals are used in conjunction with such resources as secondary
caches and the time base facility.
JTAG/COP interface signals—The common on-chip processor (COP) unit provides a serial
interface to the system for performing board-level boundary-scan interconnect tests.
Clock signals—These signals determine the system clock frequency. These signals can also be used
to synchronize multiprocessor systems.
NOTE
A bar over a signal name indicates that the signal is active low—for
example, ARTRY (address retry) and TS (transfer start). Active-low
signals are referred to as asserted (active) when they are low and negated
when they are high. Signals that are not active low, such as AP[0–3]
(address bus parity signals) and TT[0–4] (transfer type signals) are referred
to as asserted when they are high and negated when they are low.
1.1.8 Signal Configuration
Figure 4 shows the MPC750's logical pin configuration. The signals are grouped by function.
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Freescale Semiconductor, Inc.
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