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| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數(shù)： | 19/31頁 |
| 文件大?。?/td> | 318K |
| 代理商： | MPC750 |
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MPC750 RISC Microprocessor Technical Summary
19
The following tables summarize the PowerPC registers implemented in the MPC750; Table 1 describes
registers (excluding SPRs) defined by the architecture.
The OEA defines numerous special-purpose registers that serve a variety of functions, such as providing
controls, indicating status, configuring the processor, and performing special operations. During normal
execution, a program can access the registers, shown in Figure 5, depending on the program’s access
privilege (supervisor or user, determined by the privilege-level (PR) bit in the MSR). GPRs and FPRs are
accessed through operands that are part of the instructions. Access to registers can be explicit (that is,
through the use of specific instructions for that purpose such as Move to Special-Purpose Register (
mtspr
)
and Move from Special-Purpose Register (
mfspr
) instructions) or implicit, as the part of the execution of
an instruction. Some registers can be accessed both explicitly and implicitly.
In the MPC750, all SPRs are 32 bits wide. Table 2 describes the architecture-defined SPRs implemented by
the MPC750. For more information about these registers, see
PowerPC Microprocessor Family: The
Programming Environments
.
Table 1. Architecture-Defined Registers on the MPC750 (Excluding SPRs)
Register
Level
Function
CR
User
The condition register (CR) consists of eight 4-bit fields that reflect the results of certain
operations, such as move, integer and floating-point compare, arithmetic, and logical
instructions, and provide a mechanism for testing and branching.
FPRs
User
The 32 floating-point registers (FPRs) serve as the data source or destination for floating-
point instructions. These 64-bit registers can hold either single- or double-precision floating-
point values.
FPSCR
User
The floating-point status and control register (FPSCR) contains the floating-point exception
signal bits, exception summary bits, exception enable bits, and rounding control bits needed
for compliance with the IEEE-754 standard.
GPRs
User
The 32 GPRs serve as the data source or destination for integer instructions.
MSR
Supervisor The machine state register (MSR) defines the processor state. Its contents are saved when
an exception is taken and restored when exception handling completes. The MPC750
implements MSR[POW], (defined by the architecture as optional), which is used to enable the
power management feature. The MPC750-specific MSR[PM] bit is used to mark a process for
the performance monitor.
SR0–
SR15
Supervisor The sixteen 32-bit segment registers (SRs) define the 4-Gbyte space as sixteen 256-Mbyte
segments. The MPC750 implements segment registers as two arrays—a main array for data
accesses and a shadow array for instruction accesses; see Figure 1. Loading a segment
entry with the Move to Segment Register
(
mtsr
)
instruction loads both arrays. The
mfsr
instruction reads the master register, shown as part of the data MMU in Figure 1.
Table 2. Architecture-Defined SPRs Implemented by the MPC750
Register
Level
Function
LR
User
The link register (LR) can be used to provide the branch target address and to hold the
return address after branch and link instructions.
BATs
Supervisor
The architecture defines 16 block address translation registers (BATs), which operate in
pairs. There are four pairs of data BATs (DBATs) and four pairs of instruction BATs
(IBATs). BATs are used to define and configure blocks of memory.
CTR
User
The count register (CTR) is decremented and tested by branch-and-count instructions.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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