參數(shù)資料
型號(hào)： MPC750
廠商： Motorola, Inc.
英文描述： Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes
中文描述： MPC750 RISC微處理器
文件頁(yè)數(shù)： 8/31頁(yè)
文件大?。?/td> 318K
代理商： MPC750
8
MPC750 RISC Microprocessor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
branch instruction to be predicted; instructions from the second predicted instruction stream can be fetched
but cannot be dispatched.
Dynamic prediction is implemented using a 512-entry branch history table (BHT), a cache that provides two
bits per entry that together indicate four levels of prediction for a branch instruction—not-taken, strongly
not-taken, taken, strongly taken. When dynamic branch prediction is disabled, the BPU uses a bit in the
instruction encoding to predict the direction of the conditional branch. Therefore, when an unresolved
conditional branch instruction is encountered, the MPC750 executes instructions from the predicted target
stream although the results are not committed to architected registers until the conditional branch is
resolved. This execution can continue until a second unresolved branch instruction is encountered.
When a branch is taken (or predicted as taken), the instructions from the untaken path must be flushed and
the target instruction stream must be fetched into the IQ. The BTIC is a 64-entry cache that contains the
most recently used branch target instructions, typically in pairs. When an instruction fetch hits in the BTIC,
the instructions arrive in the instruction queue in the next clock cycle, a clock cycle sooner than they would
arrive from the instruction cache. Additional instructions arrive from the instruction cache in the next clock
cycle. The BTIC reduces the number of missed opportunities to dispatch instructions and gives the processor
a one-cycle head start on processing the target stream.
The BPU contains an adder to compute branch target addresses and three user-control registers—the link
register (LR), the count register (CTR), and the CR. The BPU calculates the return pointer for subroutine
calls and saves it into the LR for certain types of branch instructions. The LR also contains the branch target
address for the Branch Conditional to Link Register (
bclr
address for the Branch Conditional to Count Register (
SPRs, their contents can be copied to or from any GPR. Because the BPU uses dedicated registers rather
than GPRs or FPRs, execution of branch instructions is largely independent from execution of integer and
floating-point instructions.
x
) instruction. The CTR contains the branch target
bcctr
x
) instruction. Because the LR and CTR are
1.1.2.3 Completion Unit
The completion unit operates closely with the instruction unit. Instructions are fetched and dispatched in
program order. At the point of dispatch, the program order is maintained by assigning each dispatched
instruction a successive entry in the six-entry completion queue. The completion unit tracks instructions
from dispatch through execution and retires them in program order from the two bottom entries in the
completion queue (CQ0 and CQ1).
Instructions cannot be dispatched to an execution unit unless there is a vacancy in the completion queue.
Branch instructions that do not update the CTR or LR are removed from the instruction stream and do not
take an entry in the completion queue. Instructions that update the CTR and LR follow the same dispatch
and completion procedures as nonbranch instructions, except that they are not issued to an execution unit.
Completing an instruction commits execution results to architected registers (GPRs, FPRs, LR, and CTR).
In-order completion ensures the correct architectural state when the MPC750 must recover from a
mispredicted branch or any exception. Retiring an instruction removes it from the completion queue.
1.1.2.4 Independent Execution Units
In addition to the BPU, the MPC750 provides the five execution units described in the following sections.
1.1.2.4.1 Integer Units (IUs)
The integer units, IU1 and IU2, are shown in Figure 1. The IU1 can execute any integer instruction; the IU2
can execute any integer instruction except multiplication and division instructions. Each IU has a single-
entry reservation station that can receive instructions from the dispatch unit and operands from the GPRs or
the rename buffers.
F
Freescale Semiconductor, Inc.
n
.
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