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參數(shù)資料
| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數(shù)： | 24/31頁 |
| 文件大?。?/td> | 318K |
| 代理商： | MPC750 |
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MPC750 RISC Microprocessor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
Although multiple exception conditions can map to a single exception vector, a more specific condition may
be determined by examining a register associated with the exception—for example, the DSISR and the
FPSCR. Additionally, some exception conditions can be enabled or disabled explicitly by software.
The PowerPC architecture requires that exceptions be handled in program order; therefore, although a
particular implementation may recognize exception conditions out of order, they are handled in order. When
an instruction-caused exception is recognized, any unexecuted instructions that appear earlier in the
instruction stream, including any that are undispatched, are required to complete before the exception is
taken, and any exceptions those instructions cause must also be handled first. Likewise, asynchronous,
precise exceptions are recognized when they occur, but are not handled until the instructions currently in the
completion queue successfully retire or generate an exception, and the completion queue is emptied.
Unless a catastrophic condition causes a system reset or machine check exception, only one exception is
handled at a time. For example, if one instruction encounters multiple exception conditions, those conditions
are handled sequentially. After the exception handler handles an exception, the instruction processing
continues until the next exception condition is encountered. Recognizing and handling exception conditions
sequentially guarantees that exceptions are recoverable.
When an exception is taken, information about the processor state before the exception was taken is saved
in SRR0 and SRR1. Exception handlers should save the information stored in SRR0 and SRR1 early to
prevent the program state from being lost due to a system reset and machine check exception or to an
instruction-caused exception in the exception handler, and before enabling external interrupts.
The PowerPC architecture supports four types of exceptions:
Synchronous, precise—These are caused by instructions. All instruction-caused exceptions are
handled precisely; that is, the machine state at the time the exception occurs is known and can be
completely restored. This means that (excluding the trap and system call exceptions) the address of
the faulting instruction is provided to the exception handler and that neither the faulting instruction
nor subsequent instructions in the code stream will complete execution before the exception is
taken. Once the exception is processed, execution resumes at the address of the faulting instruction
(or at an alternate address provided by the exception handler). When an exception is taken due to a
trap or system call instruction, execution resumes at an address provided by the handler.
Synchronous, imprecise—The PowerPC architecture defines two imprecise floating-point
exception modes, recoverable and nonrecoverable. Even though the MPC750 provides a means to
enable the imprecise modes, it implements these modes identically to the precise mode (that is,
enabled floating-point exceptions are always precise).
Asynchronous, maskable—The PowerPC architecture defines external and decrementer interrupts
as maskable, asynchronous exceptions. When these exceptions occur, their handling is postponed
until the next instruction, and any exceptions associated with that instruction, completes execution.
If no instructions are in the execution units, the exception is taken immediately upon determination
of the correct restart address (for loading SRR0). As shown in Table 4, the MPC750 implements
additional asynchronous, maskable exceptions.
Asynchronous, nonmaskable—There are two nonmaskable asynchronous exceptions: system reset
and the machine check exception. These exceptions may not be recoverable, or may provide a
limited degree of recoverability. Exceptions report recoverability through the MSR[RI] bit.
F
Freescale Semiconductor, Inc.
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