參數(shù)資料
型號(hào): MPC603RVG300LC
廠商: Freescale Semiconductor
文件頁數(shù): 9/31頁
文件大小: 0K
描述: MPU RISC PID7V-603E 255FCCBGA
標(biāo)準(zhǔn)包裝: 60
系列: MPC6xx
處理器類型: 32-位 MPC603e PowerPC
速度: 300MHz
電壓: 2.5V
安裝類型: 表面貼裝
封裝/外殼: 255-BCBGA 裸露焊盤,255-FCCBGA
供應(yīng)商設(shè)備封裝: 255-FCCBGA(21x21)
包裝: 托盤
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
17
Package Descriptions
7
Package Descriptions
The following sections provide the CBGA and PBGA package parameters and the mechanical dimensions
for the 603e.
7.1
CBGA Package Description
The following sections provide the package parameters and mechanical dimensions for the CBGA
package.
7.1.1
Package Parameters
The package parameters are as provided in the following list. The package type is 21 mm x 21 mm,
255-lead ceramic ball grid array (CBGA).
Package outline
21 mm x 21 mm
Interconnects
255
Pitch
1.27 mm (50 mil)
Package height
Minimum: 2.45 mm
Maximum: 3.00 mm
Ball diameter
0.89 mm (35 mil)
Maximum heat sink force
10 lbs
TS
J13
Low
I/O
TSIZ[0–2]
A13, D10, B12
High
O
TT[0–4]
B13, A15, B16, C14, C15
High
I/O
WT
D02
Low
O
VDD
2
F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11, K07, K10, L06,
L08, L09, L11
——
VOLTDETGND 3
F03
Low
O
Note:
1. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation.
2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core.
3. NC (no-connect) in the PID6-603e; internally tied to GND in the PID7v-603e and PID7t-603e CBGA and PBGA package to
indicate to the power supply that a low-voltage processor is present.
Table 11. Pinout Listing for the 255-Pin CBGA and PBGA Packages (continued)
Signal Name
Pin Number
Active
I/O
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