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| 型號： | MPC603RVG300LC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 29/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU RISC PID7V-603E 255FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | MPC6xx |
| 處理器類型： | 32-位 MPC603e PowerPC |
| 速度： | 300MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 255-BCBGA 裸露焊盤，255-FCCBGA |
| 供應(yīng)商設(shè)備封裝： | 255-FCCBGA（21x21） |
| 包裝： | 托盤 |
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PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
7
Electrical and Thermal Characteristics
4.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the PID7t-603e. These specifications are for 200,
266, and 300 MHz processor speed grades. The processor core frequency is determined by the bus
(SYSCLK) frequency and the settings of the PLL_CFG[0–3] signals. All timings are specified respective
to the rising edge of SYSCLK. PLL_CFG signals should be set prior to power up and not altered
afterwards.
4.2.1
Clock AC Specifications
This table provides the clock AC timing specifications as defined in Figure 1. After fabrication, parts are
sorted by maximum processor core frequency as shown in Section 4.2.1, “Clock AC Specifications,” and
tested for conformance to the AC specifications for that frequency. Parts are sold by maximum processor
core frequency; see Section 9, “Ordering Information.”
Typical
40
mW
Sleep Mode—PLL and SYSCLK Disabled
Typical
15
mW
Maximum
25
80
100
mW
Note:
1. These values apply for all valid PLL_CFG[0–3] settings and do not include output driver power (OVdd) or analog supply
power (AVdd). OVdd power is system dependent but is typically 10% of Vdd. Worst-case AVdd = 15 mW.
2. Typical power is an average value measured at Vdd = AVdd = 2.5 V, OVdd = 3.3V, in a system executing typical applications
and benchmark sequences.
3. Maximum power is measured at 2.625 V using a worst-case instruction mix.
Table 7. Clock AC Timing Specifications
Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 Tj 105 °C
Num
Characteristic
200 MHz
PBGA
200 MHz
CBGA
266 MHz
CBGA
300 MHz
CBGA
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Processor frequency
100
200
80
200
150
266
180
300
MHz
1, 6
VCO frequency
300
400
300
400
300
532
360
600
MHz
1
SYSCLK frequency
25
66.67
25
66.67
25
75
33.3
75
MHz
1
SYSCLK cycle time
13.3
40
13.3
40
13.3
40
13.3
30
ns
2, 3
SYSCLK rise and fall time
—
2.0
—
2.0
—
2.0
—
2.0
ns
2
4
SYSCLK duty cycle measured
at 1.4 V
40.0
60.0
40.0
60.0
40.0
60.0
40.0
60.0
%
3
Table 6. Power Consumption (continued)
Processor (CPU) Frequency
Unit
100 MHz
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
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