參數(shù)資料
型號: MPC603RVG300LC
廠商: Freescale Semiconductor
文件頁數(shù): 3/31頁
文件大?。?/td> 0K
描述: MPU RISC PID7V-603E 255FCCBGA
標準包裝: 60
系列: MPC6xx
處理器類型: 32-位 MPC603e PowerPC
速度: 300MHz
電壓: 2.5V
安裝類型: 表面貼裝
封裝/外殼: 255-BCBGA 裸露焊盤,255-FCCBGA
供應商設備封裝: 255-FCCBGA(21x21)
包裝: 托盤
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
11
Electrical and Thermal Characteristics
This figure provides the output timing diagram for the PID7t-603e.
Figure 4. Output Timing Diagram
4.3
JTAG AC Timing Specifications
This table provides the JTAG AC timing specifications as defined in Figure 5–Figure 8.
Note:
1. All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or 2.0 V) of the
signal in question. Both input and output timings are measured at the pin (see Figure 4).
2. This minimum parameter assumes CL = 0 pF.
3. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external voltage from 5.5 V
to 0.8 V instead of from Vdd to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS levels).
4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied
by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
5. Output signal transitions from GND to 2.0 V or Vdd to 0.8 V.
6. Nominal precharge width for ABB and DBB is 0.5
t
sysclk.
7. Nominal precharge width for ARTRY is 1.0
t
sysclk.
Table 9. Output AC Timing Specifications1 (continued)
Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 ± 5%, GND = 0 V dc, 0 Tj 105 °C, CL = 50 pF (unless otherwise noted)
Num
Characteristic
200, 266, 300 MHz
Unit
Note
Min
Max
SYSCLK
12
14
13
15
16
TS
ARTRY
ABB, DBB
VM
VM = Midpoint Voltage (1.4 V)
VM
13
20
18
17
21
19
15
16
ALL OUTPUTS
(Except TS, ABB,
DBB, ARTRY)
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