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參數(shù)資料
| 型號： | MN89306 |
| 廠商： | PANASONIC CORP |
| 元件分類： | 顯示控制器 |
| 英文描述： | 800 X 600 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128 |
| 封裝： | 18 X 18 MM, PLASTIC, LQFP-128 |
| 文件頁數(shù)： | 6/47頁 |
| 文件大小： | 487K |
| 代理商： | MN89306 |
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MN89306
LSIs for Display
14
Pin Name
I/O
Level
Function
MA11
O
Display memory address
MA[10 : 0]
I/O
CMOS
Display memory address
These pins are set to input mode by a reset, and the pins MA[2:0] are used to set
the chip host type. The pins MA[9:3] are latched internally to the IC as the
expansion pin monitor register data. Pull up the MA10 pin if SDRAM is used.
16M DRAM
RAS address: MA[10:0], CAS address: MA[7:0]
MA11: Bank select
4M DRAM
RAS address: MA[8:0], CAS address: MA[7:0]
MA9: Bank select, MA[11:10]: Low-level output
MCLK
O
Memory clock
SDRAM operating clock.
MCS
#
O
Chip select
SDRAM command signal.
RAS
#
O
Row address strobe
Row address strobe output.
CAS
#
O
Column address strobe
Column address strobe output.
WE
#
O
Write enable
Data write signal output.
LDQM
O
Low data
Low-order byte output mask signal.
HDQM
O
High data
High-order byte output mask signal.
MCLKEN
O
Memory clock enable
Sets the SDRAM to the operating state. This pin outputs a high level during normal
operation, but is set to low in suspend and sleep modes.
This pin cannot be used in external RAMDAC mode. In that mode, tie the SDRAM
CLKEN pin high.
Note that both suspend and sleep mode cannot be used with external
RAMDAC mode.
MD[15 : 0]
I/O
CMOS
Memory data bus
DRAM memory data.
s Pin Descriptions (continued)
4) Memory Access Related Pins (continued)
When SDRAM is used.
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